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| To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS07-13505-5E 16-bit Proprietary Microcontroller CMOS F2MC-16F MB90246A Series MB90246A s DESCRIPTION The MB90246A series is a 16-bit microcontroller optimum to control mechatronics such as a hard disk drive unit. The instruction set of F2MC-16F CPU core inherits AT architecture of F2MC*-16/16H family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data (32-bit). The MB90246A series contains a production addition unit as peripheral resources for enabling easy implementation of functions supported by IIR and FIR digital filters. It also supports a wealth of peripheral functions including: - an 8/10-bit A/D converter having eight channels; - an 8-bit D/A converter having three channels; - UART; - an 8-bit PWM timer having four channels; - a timer having three plus one channels; - an input capture (ICU) having two channels; and - a DTP/external interrupt circuit having four channels. * : F2MC stands for FUJITSU Flexible Microcontroller. s PACKAGE 100-pin Plastic LQFP (FPT-100P-M05) To Top / Lineup / Index MB90246A Series s FEATURES * Clock Operating clock can be selected from divided-by-2, 4, 8 or 32 of oscillation (at oscillation of 32 MHz, 1 MHz to 16 MHz). Minimum instruction execution time of 62.5 ns (at machine clock of 16 MHz) * CPU addressing space of 16 Mbytes Internal addressing of 24-bit External accessing can be performed by selecting 8/16-bit bus width (external bus mode) * Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) High code efficiency Enhanced precision calculation realized by the 32-bit accumulator Signed multiplication/division instruction * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Enhanced execution speed 8-byte instruction queue * Enhanced interrupt function Priority levels: 8 levels External interrupt input ports: 4 ports * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) Hardware stand-by mode Gear function * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 38 General-purpose I/O ports (TTL): 11 General-purpose I/O ports (N-ch open-drain): 8 Total: 57 * Timer Timebase timer/watchdog timer: 1 channel 8-bit PWM timer: 4 channels 16-bit re-load timer: 3 channels * 16-bit I/O timer 16-bit free-run timer: 1 channel Input capture (ICU): 2 channels * I/O simple serial interface Clock synchronized transmission can be used. * UART: 1 channel Clock asynchronized or clock synchronized serial transmission can be selectively used. * DTP/external interrupt circuit: 4 channels A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. (Continued) 2 To Top / Lineup / Index MB90246A Series (Continued) * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter: 8 channels 8-bit or 10-bit resolution can be selectively used. Starting by an external trigger input. * 8-bit D/A converter Resolution: 8 bits x 3 channels * DSP interface for the IIR filter Function dedicated to IIR calculation Up to eight items of results of signed multiplication of 16 x 16 bits are added. N M Execution time of Yk = bn Yk - n + am Xk - m : 0.625 s (When oscillation is 32 MHz and when N = M =3) n=0 m=0 Up to three N and M values can be set at your disposal. 3 To Top / Lineup / Index MB90246A Series s PRODUCT LINEUP Part number Item Classification ROM size RAM size 4 k x 8 bits MB90246A Mass-produced product None 6 k x 8 bits MB90V246 Evaluation product CPU functions The number of instructions: 412 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 4 bits, 8 bits, 16 bits, 32 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.0 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 38 General-purpose I/O ports (TTL input): 11 General-purpose I/O ports (N-ch open-drain output): 8 Total: 57 18-bit counter Interrupt interval: 0.256 ms, 1.024 ms, 4.096 ms, 16.384 ms (at oscillation of 32 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 28.67 ms, 57.34 ms (at oscillation of 32 MHz, minimum value) Number of channels: 4 Pulse interval: 0.25 s to 32.77 ms (at oscillation of 32 MHz) Number of channels: 3 16-bit re-load timer operation Interval: 125 ns to 131 ms (at machine clock of 16 MHz) External event count can be performed. Number of channel: 1 Overflow interrupts or intermediate bit interrupts may be generated. Number of channel: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of channels: 2 Clock synchronized transmission (62.5 kbps to 8 Mbps) Clock asynchronized transmission (2404 bps to 500 kbps) Clock synchronized transmission (250 kbps to 2 Mbps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Number of inputs: 4 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. An interrupt generation module for switching tasks used in real-time operating systems. Ports Timebase timer Watchdog timer 8/16-bit PWM timer 16-bit re-load timer 16-bit I/O timer 16-bit free-run timer Input capture (ICU) I/O simple serial interface UART DTP/external interrupt circuit Delayed interrupt generation module (Continued) 4 To Top / Lineup / Index MB90246A Series (Continued) Part number Item Conversion precision: 10-bit or 8-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 3 Resolution: 8 bits Based on the R-2R system Function dedicated to IIR calculation Up to 8 items of results of signed multiplication of 16 x 16 bits are added. N M Execution time of Yk = bn Yk - n + am Xk - m : 0.625 s n=0 m=0 (When oscillation is 32 MHz and when N = M = 3) Up to three N and M values can be set at your disposal. Sleep/stop/hardware stand-by/gear function CMOS 4.5 V to 5.5 V MB90246A MB90V246 8/10-bit A/D converter 8-bit D/A converter DSP interface for the IIR filter Low-power consumption (stand-by) mode Process Power supply voltage for operation* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") Assurance for the MB90V246 is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 to 70 degrees centigrade, and an clock frequency of 1.6 MHz to 32 MHz. Note: A 64-word RAM for product addition is supported in addition to the above RAMs. s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-100P-M05 PGA-256C-A02 : Available x : Not available x MB90246A MB90V246 x Note: For more information about each package, see section "s Package Dimensions." s DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used. The RAM size is 4 Kbytes for the MB90246A, and 6 Kbytes for the MB90V246. 5 To Top / Lineup / Index MB90246A Series s PIN ASSIGNMENT (Top view) A01 A00 P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D09 P10/D08 P07 P06 P05 P04 P03 P02 P01 P00 VCC X1 X0 VSS P57 P56/RD P55/WR/WRL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A02 A03 A04 A05 A06 A07 A08 A09 VSS A10 A11 A12 A13 A14 A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/A20 VCC P45/A21 P46/A22 P47/A23 P70/ASR0 RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA5/SCK2 PA4/SOD2 PA3/SID2 PA2/SCK1 PA1/SOD1 PA0/SID1 P96/SCK0 P95/SOD0 P94/SID0 P93/INT3/PWM3 P92/INT2/ATG P91/INT1 P90/INT0 P87/PWM2 P86/PWM1 P85/PWM0 P84/DAO2 P83/DAO1 P82/DAO0 6 P71/ASR1 P72 P73 P74/TIN0/TOT0 P75/TIN1/TOT1 P76/TIN2/TOT2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 DVRH DVRL MD0 MD1 MD2 HST (FPT-100P-M05) To Top / Lineup / Index MB90246A Series s PIN DESCRIPTION Pin no. LQFP* 80 81 47 to 49 75 50 91 to 98 X0 X1 MD0 to MD2 RST HST P10 to P17 C B C D This is an input pin for selecting operation modes. Connect directly to VCC or VSS. This is external reset request signal. This is a hardware stand-by input pin. This is a general-purpose I/O port. This function is valid in the 8-bit mode where the external bus is valid. This is an I/O pin for the upper 8-bit of the external address data bus. This function is valid in the 16-bit mode where the external bus is valid. E This is a general-purpose I/O port. This function becomes valid in the bit where the upper address control register is set to select a port. This is an output pin for the upper 8-bit of the external address bus. This function is valid in the mode where the external bus is valid and the upper address control register is set to select an address. E This is a general-purpose I/O port. This function becomes valid when the CLK output is disabled. This is a CLK output pin. This function becomes valid when CLK output is enabled. D This is a general-purpose I/O port. This function becomes valid when the external ready function are disabled. This is a ready input pin. This function becomes valid when the external ready function is enabled. D This is a general-purpose I/O port. This function becomes valid when the hold function are disabled. This is a hold acknowledge output pin. This function becomes valid when the hold function is enabled. D This is a general-purpose I/O port. This function becomes valid when the hold function are disabled. This is a hold request input pin. This function becomes valid when the hold function is enabled. E This is a general-purpose I/O port. This function becomes valid, in the external bus 8-bit mode, or WRH pin output is disabled. This is a write strobe output pin for the upper 8-bit of the data bus. This function becomes valid when the external bus 16-bit mode is selected, and WRH output pin is enabled. Pin name Circuit type A Function This is a crystal oscillator pin. D08 to D15 16 to 20, 22 to 24 P40 to P44, P45 to P47 A16 to A20, A21 to A23 70 P50 CLK 71 P51 RDY 72 P52 HAK 73 P53 HRQ 74 P54 WRH * : FPT-100P-M05 (Continued) 7 To Top / Lineup / Index MB90246A Series Pin no. LQFP* 76 P55 WR Pin name Circuit type E Function This is a general-purpose I/O port. This function becomes valid when WRL/WR pin output is disabled. This is a write strobe output pin for the lower 8-bit of data bus. This function becomes valid when WRL/WR pin output is enabled. WRL is used for holding the lower 8-bit for write strobe in 16-bit access operations, while WR is used for holding 8-bit data for write strobe in 8-bit access operations. WRL 77 P56 RD E This pin cannot be used as a general-purpose port. This is a read strobe output pin for the data bus. This function is valid in the mode where the external bus is valid. 78, 28, 27 36 to 39, 41 to 44 P57, P73, P72 P60 to P63, P64 to P67 E This is a general-purpose I/O port. G This is an I/O port of an N-ch open-drain type. When the data register is read by a read instruction other than the modify write instruction with the corresponding bit in ADER set at "0", the pin level is acquired. The value set in the data register is output to the pin as is. This is an analog input pin of the 8/10-bit A/D converter. When using this input pin, set the corresponding bit in ADER at "1". Also, set the corresponding bit in the data register at "1". AN0 to AN3, AN4 to AN7 25 P70 ASR0 E This is a general-purpose I/O port. This is a data input pin for input capture 0. Because this input is used as required when the input capture 0 is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. 26 P71 ASR1 E This is a general-purpose I/O port. This is a data input pin of input capture 1. Because this input is used as required when input capture 1 is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. 29 to 31 P74 to P76 E This is a general-purpose I/O port. This function becomes valid when outputs from 16-bit re-load timer 0 - 2 are disabled. This is an input pin of 16-bit timer. Because this input is used as required whin 16-bit timer 0 - 2 is performing input operations,and it is necessary to stop outputs by other functions unless such outputs are made intentionally. These are output pins for 16-bit re-load timer 0 and 1. This function becomes valid when output from 16-bit re-load timer 0 - 2 are enabled. TIN0 to TIN 2 TOT0 to TOT2 51 to 53 P82 to P84 H This is a general-purpose I/O port. This function becomes valid when data output from 8-bit D/A converter 0 - 2 are disabled. This is an output pin of 8-bit D/A converter. This function becomes valid when data output from 8-bit D/A converter 0 - 2 are enabled. (Continued) DAO0 to DAO2 * : FPT-100P-M05 8 To Top / Lineup / Index MB90246A Series Pin no. LQFP* 54 to 56 Pin name P85 to P87 Circuit type E Function This is a general-purpose I/O port. This function becomes valid when output from PWM0 - PWM2 are disabled. This is an output pin of 8-bit PWM timer. This function becomes valid when output from PWM0 - PWM2 are enabled. PWM0 to PWM2 57, 58 P90, P91 INT0, INT1 F This is a general-purpose I/O port. This is a request input pin of the DTP/external interrupt circuit ch.0 and 1. Because this input is used as required when the DTP/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. 59 P92 INT2 E This is a general-purpose I/O port. This is an input pin of the DTP/external interrupt circuit ch.2. Because this input is used as required when the DTP/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. This is a trigger input pin of the 8/10-bit A/D converter. Because this input is used as requited when the 8/10-bit A/D converter is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. ATG 60 P93 E This is a general-purpose I/O port. This function is always valid. This function becomes valid when output from PWM3 is disabled. This is a request input of the DTP/external interrupt circuit ch. 3. Because this input is used as required when the DTP/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such output are made intentionally. This is an output pin of 8-bit PWM timer. This function becomes valid when output from PWM3 is enabled. INT3 PWM3 61 P94 E This is a general-purpose I/O port. This function becomes valid when serial data output from UART is disabled. This is a serial data I/O pin of UART. This function becomes valid when serial data output from UART is enabled. Because this input is used as required when UART is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. SID0 * : FPT-100P-M05 (Continued) 9 To Top / Lineup / Index MB90246A Series Pin no. LQFP* 62 P95 Pin name Circuit type E Function This is a general-purpose I/O port. This function becomes valid when data output from UART is disabled. This is a data output pin of UART. This function becomes valid when data output from UART is enabled. SOD0 63 P96 E This is a general-purpose I/O port. This function becomes valid when clock output from UART is disabled. This is a clock I/O pin of UART. This function becomes valid when clock output from UART is enabled. Because this input is used as required when UART is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. SCK0 1 to 6, 100, 99 7, 8, 10 to 15 64 A02 to A07, A01, A00 A08, A09, A10 to A15 PA0 SID1 E This is an output pin for the lower 8-bit of the external address bus. E This is an output pin for the middle 8-bit of the external address bus. This function is valid in the mode where the external bus is valid and the middle address control refister is set to select an address. This is a general-purpose I/O port. This is a data input pin of I/O simple serial interface 1. Because this input is used as required when I/O simple serial interface 1 is performing input operations, and it is necessarey to stop outputs by other functions unless such outputs are made intentionally. E 65 PA1 E This is a general-purpose I/O port. This function becomes valid when data output from I/O simple serial interface 1 is disabled. This is a data output pin of I/O simple serial interface 1. This function becomes valid when data output from I/O simple serial interface 1 is enabled. SOD1 66 PA2 E This is a general-purpose I/O port. This function becomes valid when clock output from I/O simple serial interface 1 is disabled. This is a clock output pin of I/O simple serial interface 1. This function becomes valid when clock output from I/O simple serial interface 1 is enabled. SCK1 * : FPT-100P-M05 (Continued) 10 To Top / Lineup / Index MB90246A Series (Continued) Pin no. LQFP* 67 PA3 SID2 Pin name Circuit type E Function This is a general-purpose I/O port. This is a data input pin of I/O simple serial interface 2. Because this input is used as required when is performing input operations, and it is I/O simple serial interface 2 necessarey to stop outputs by other functions unless such outputs are made intentionally. 68 PA4 E This is a general-purpose I/O port. This function becomes valid when data output from I/O simple serial interface 2 is disabled. This is a data output pin of I/O simple serial interface 2. This function becomes valid when data output from I/O simple serial interface 2 is enabled. SOD2 69 PA5 E This is a general-purpose I/O port. This function becomes valid when clock output from I/O simple serial interface 2 is disabled. This is clock output pin of I/O simple serial interface 2. This function becomes valid when clock output from I/O simple serial interface 2 is enabled. SCK2 83 to 90 21, 82 9, 40, 79 32 D00 to D07 VCC VSS D Power supply Power supply Power supply Power supply Power supply Power supply Power supply Power supply This is an I/O pin for the lower 8-bit of the external data bus. This is power supply to the digital circuit. This is a ground level of the digital circuit. AVCC This is power supply to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVCC applied to VCC. This is a reference voltage input to the A/D converter. Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AVCC. This is a reference voltage input to the A/D converter. This is a ground level of the analog circuit. This is an external reference power supply pin for the D/A converter. This is an external reference power supply pin for the D/A converter. 33 AVRH 34 35 45 46 AVRL AVSS DVRH DVRL * : FPT-100P-M05 11 To Top / Lineup / Index MB90246A Series s I/O CIRCUIT TYPE Type A Clock suspension X1 Circuit Remarks * For oscillation of 32 MHz * Oscillation feedback resistor approx. 1 M N-ch X0 Clock input B VCC P-ch type trigger * CMOS level hysteresis input (without stand-by control) * Pull-up resistor approx. 50 K R VSS CMOS N-ch type trigger Digital input C VCC P-ch type trigger * CMOS level hysteresis input (without stand-by control) R VSS CMOS N-ch type trigger Digital input D Digital output * CMOS level output * TTL level input (with stand-by control) P-ch R N-ch Digital output Digital input TTL Standby control signal (Continued) 12 To Top / Lineup / Index MB90246A Series (Continued) Type E P-ch Digital output R N-ch Circuit Remarks * CMOS level output * CMOS level hysteresis input (with stand-by control) Digital output Digital input CMOS Standby control signal F P-ch Digital output * CMOS level input * CMOS level hysteresis input (with stand-by control (during interrupt disable)) R N-ch Digital output Digital input Standby control signal (during interrupt disable) G R * * * * Digital output Analog input Digital input N-ch open-drain CMOS level output CMOS level hysteresis input Analog input (with analog control) ADER CMOS H P-ch Digital output Digital output Analog input Digital input * CMOS level output * Analog output * CMOS level hysteresis input (with stand-by control) R N-ch Standby control signal CMOS 13 To Top / Lineup / Index MB90246A Series s HANDLING DEVICES 1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up) In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH) and analog input voltages not exceed the digital voltage (VCC). 2. Connection of Unused Pins Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down resistor. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock X0 Open X1 MB90246A series 4. Power Supply Pins In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 14 To Top / Lineup / Index MB90246A Series 6. Turning-on Sequence of Power Supply to A/D Converter, D/A Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL), D/A converter power supply and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 8. "MOV @AL, AH", "MOVW @AL, AH" Instructions When the above instruction is performed to I/O space, an unnecessary writing operation may be performed (#FF, #FFFF) in the internal bus. Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing operation. Accessing RAM space with the above instruction does not cause any problem. 9. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. 10.External Reset Input To reset the internal securely, "L" level input to the RST pin must be at least 5 machine cycle. 11.HST Pin Make sure HST pin is set to "H" level when turn on the power supply. Also make sure HST pin is never set to "L" level, when RST pin is set to "L" level. 12.CLK Pin X1 a case 32 MHz X0 STOP To the inside 2 deviding circuit P50/CLK* P50 output P50 input CLK output *: At P50/CLK pin in the external bus mode, CLK output is selected as an initial value. 15 To Top / Lineup / Index MB90246A Series s BLOCK DIAGRAM F2MC-16F. CPU Interrupt controller X0 X1 RST HST 8 8 16 8 8 2 13 Clock control block (including timebase timer) 8-bit D/A converter DVRH DVRL 3 3 P82/DAO0 to P84/DAO2 P10/D08 to P17/D15 A00 to A15 D00 to D07 P40/A16 to P47/A23 P50/CLK P51/RDY P52/HAK P53/HRQ P54/WRH P55/WR/WRL P56/RD P57 P72 P73 Port 1 Port 8 3 3 External bus interface 8-bit PWM timer x 4 channels DTP/external interrupt circuit 3 Port 9 2 UATR P85/PWM0 to P87/PWM2 P93/INT3/PWM3 Port 4, 5 Internal data bus Port 7 3 16-bit re-load timer 16-bit I/O timer 3 2 Input compare (ICU) P94/SID0 P95/SOD0 P96/SCK0 P74/TIN0/TOT0 to P76/TIN2/TOT2 P70/ASR0 P71/ASR1 3 4 I/O simple serial 2 interface PA0/SID1 PA1/SOD1 PA2/SCK1 PA3/SID2 PA4/SOD2 PA5/SCK2 Port A 16-bit free-run timer P90/INT0 P91/INT1 3 DTP/external interrupt circuit 0, 1, 2 Port 9 DSP interface for the IIR filter P92/INT2/ATG AVRH AVRL AVCC AVSS 8 P60/AN0 to P67/AN7 Other pins MD0 to MD2, VCC,VSS 8 Port 6 RAM 8/10-bit A/D converter 16 To Top / Lineup / Index MB90246A Series MEMORY MAP External ROM external bus mode FFFFFFH External area 001980H 001900H 001100H I/O External area RAM Register 000100H External area 0000C0H 000000H I/O : Internal access memory : Enternal access memory The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". 17 To Top / Lineup / Index MB90246A Series s F2MC-16F CPU PROGRAMMING MODEL (1) Dedicated Registers AH AL : Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer for containing a user stack address. : System stack pointer (SSP) The 16-bit pointer for displaying the status of the system stack address. : Processor status (PS) The 16-bit register for displaying the system status. : Program counter (PC) The 16-bit register for displaying storing location of the current instruction code. USPCU : User stack upper limit register (USPCU) The 16-bit register for specifying the upper limit of the user stack. : System stack upper limit register (SSPCU) The 16-bit register for specifying the upper limit of the system stack. : User stack lower limit register (USPCL) The 16-bit register for specifying the lower limit of the user stack. : System stack lower limit register (SSPCL) The 16-bit register for specifying the lower limit of the system stack. : Direct page register (DPR) The 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register for displaying the program space. : Data bank register (DTB) The 8-bit register for displaying the data space. : User stack bank register (USB) The 8-bit register for displaying the user stack space. : System stack bank register (SSB) The 8-bit register for displaying the system stack space. : Additional data bank register (ADB) The 8-bit register for displaying the additional data. USP SSP PS PC SSCPU USPCL SSPCL DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit 18 To Top / Lineup / Index MB90246A Series (2) General-purpose Registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180 H + (RP x 10 H ) RW0 16-bit (3) Processor Status (PS) ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value -- : Unused X : Indeterminate ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0 19 To Top / Lineup / Index MB90246A Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH to 00001FH 000020H 000021H 000022H 000023H SCR1 SSR1 SDR1L SDR1H Serial status register 1 Serial data register 1 (L) Serial data register 1 (H) DDR4 DDR5 ADER DDR7 DDR8 DDR9 DDRA DDR1 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDR1 Abbreviated register name Register name Read/ write Resource name Initial value (System reservation area)*1 Port 1 data register R/W! Port 1 XXXXXXXXB (System reservation area)*1 Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register R/W! R/W! R/W! R/W! R/W! R/W! R/W! (Vacancy) (System reservation area)*1 Port 1 direction register R/W Port 1 00000000B Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A XXXXXXXXB XXXXXXXXB 11111111B - XXXXXXXB XXXXXX - - B - XXXXXXXB - - XXXXXXB (System reservation area)*1 Port 4 direction register Port 5 direction register Analog input enable register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register R/W R/W R/W R/W R/W R/W R/W (Vacancy) Serial control status register 1 R/W R R/W R/W I/O simple serial interface 1 10000000B -------1B XXXXXXXXB XXXXXXXXB Port 4 Port 5 Port 6, 8/10-bit A/D converter Port 7 Port 8 Port 9 Port A 00000000B 00000000B 11111111B -0000000B 000000--B - XXXXXXXB --000000B (Continued) 20 To Top / Lineup / Index MB90246A Series Address 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H Abbreviated register name SCR2 SSR2 SDR2L SDR2H UMC USR UIDR/ UODR URD PWMC3 Register name Serial control status register 2 Serial status register 2 Serial data register 2 (L) Serial data register 2 (H) Mode control register Status register Input data register/ output data register Rate and data register PWM3 operating mode control register PWM3 re-road register (L) PWM3 re-road register (H) DTP/interrupt enable register DTP/interrupt factor register Request level setting register PWM0 operating mode control register PWM0 re-road register (L) PWM0 re-road register (H) PWM1 operating mode control register PWM1 re-road register (L) PWM1 re-road register (H) PWM2 operating mode control register PWM2 re-road register (L) PWM2 re-road register (H) Timer control status register 0 lower digits Timer control status register 0 upper digits Read/ write R/W R R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 10000000B I/O simple serial interface 2 -------1B XXXXXXXXB XXXXXXXXB 00000100B 00010000B UART XXXXXXXXB 00000000B 8-bit PWM timer 3 0 0 0 0 0XX1 B (Vacancy) PRLL3 PRLH3 ENIR EIRR ELVR R/W R/W R/W R/W R/W 8-bit PWM timer 0 DTP/external interrupt circuit 8-bit PWM timer 3 XXXXXXXXB XXXXXXXX B ----0000B ----0000B 00000000B (Vacancy) PWMC0 R/W 0 0 0 0 0XX1 B (Vacancy) PRLL0 PRLH0 PWMC1 R/W R/W R/W 8-bit PWM timer 0 8-bit PWM timer 1 XXXXXXXXB XXXXXXXX B 0 0 0 0 0XX1 B (Vacancy) PRLL1 PRLH1 PWMC2 R/W R/W R/W 8-bit PWM timer 1 8-bit PWM timer 2 XXXXXXXXB XXXXXXXX B 0 0 0 0 0XX1 B (Vacancy) PRLL2 PRLH2 R/W R/W R/W R/W 8-bit PWM timer 2 16-bit re-load timer 0 XXXXXXXXB XXXXXXXX B 00000000B ----0000B TMCSR0 000041H (Continued) 21 To Top / Lineup / Index MB90246A Series Address 000042H 000043H 000044H 000045H 000046H 000047H 000048H Abbreviated register name TMR0 TMRLR0 Register name 16-bit timer register 0 16-bit re-load register 0 Read/ write R Resource name Initial value XXXXXXXXB 16-bit re-load timer 0 R/W (Vacancy) Timer control status register 1 lower digits Timer control status register 1 upper digits 16-bit timer register 1 16-bit re-load register 1 R/W R/W R R/W (Vacancy) Timer control status register 2 lower digits Timer control status register 2 upper digits 16-bit timer register 2 16-bit re-load register 2 R/W R/W R R/W 16-bit re-load timer 2 16-bit re-load timer 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B ----0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB TMCSR1 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H TMCSR2 000051H 000052H 000053H 000054H 000055H 000056H to 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 22 DADR0 DACR0 DADR1 DACR1 DADR2 DACR2 IPCP0 IPCP1 ICS0 TMR2 TMRLR2 TMR1 TMRLR1 00000000B ----1111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Vacancy) D/A data register 0 D/A control register 0 D/A data register 1 D/A control register 1 D/A data register 2 D/A control register 2 Input capture register 0 Input capture register 1 Input capture control register R/W R/W R/W R/W R/W R/W R R R/W 16-bit I/O timer (input capture 0, 1) 8-bit D/A converter 0 8-bit D/A converter 1 8-bit D/A converter 2 XXXXXXXXB -------0B XXXXXXXXB -------0B XXXXXXXXB -------0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B (Continued) To Top / Lineup / Index MB90246A Series Address 000065H to 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH to 00007FH 000080H Abbreviated register name Register name Read/ write (Vacancy) Resource name Initial value TCDT TCCS Timer data register Timer control status register A/D control status register lower digits A/D control status register upper digits Conversion time setting register A/D data register 0 A/D data register 1 A/D data register 2 A/D data register 3 R/W R/W 16-bit I/O timer (16-bit free-run timer) 00000000B 00000000B 00000000B (Vacancy) ADCSL ADCSH ADCT ADTL0 ADTH0 ADTL1 ADTH1 ADTL2 ADTH2 ADTL3 ADTH3 R/W R/W R/W R R R R R R R R (Vacancy) Product addition control status register lower digits Product addition control status register digits Product addition continuation control register lower digits Product addition continuation control register upper digits R/W R/W R/W R/W R Production addition output register R R DSP interface for the IIR filter XXX 0 XXX 0 B - XXXXXXXB 00000000B ------00B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 000-0000B -000--00B XXXXXXXXB XXXXXXXXB 8/10-bit A/D converter XXXXXXXXB ------* * ------* * ------* * ------* * B XXXXXXXXB B XXXXXXXXB B XXXXXXXXB B MCSR 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H MCCRL MCCRH MDORL MDORM MDORH (Continued) 23 To Top / Lineup / Index MB90246A Series (Continued) Address 000089H to 00008FH 000090H to 00009EH 00009FH DIRR Abbreviated register name Register name Read/ write (Vacancy) Resource name Initial value (System reservation area)*1 Delayed interrupt factor generation/ cancellation register Standby control register Delayed interrupt generation module Low-power consumption (stand-by) mode R/W -------0B 0000A0H 0000A1H to 0000A3H 0000A4H 0000A5H 0000A8H 0000A9H 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH STBYC R/W 0 0 0 1 XXXXB (System reservation area)*1 HACR EPCR WDTC TBTC ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Upper address control register External pin control register Watchdog timer control register Timebase timer control register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller *2 *2 XXXXXXXXB -XX0 0 1 0 0 B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B External bus pin Watchdog timer Timebase timer (External area)*3 24 To Top / Lineup / Index MB90246A Series Descriptions for read/write R/W: Readable and writable R: Read only W: Write only R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific resource for detailed information. Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is indeterminate. - : This bit is not used. The initial value is indeterminate. * : The storage type varies with the value of the ADCSH CREG bit. *1: Access prohibited. *2: The initial value varies with bus mode. *3: This area is the only external access area having an address of 0000FFH or lower. Access to any of the addresses specified as reserved areas in the table is handled as if an internal area were accessed. A signal for accessing an external bus is not generated. *4: When a register described as R/W! or W in the read/write column is accessed by a bit setting instruction or other read modify write instructions, the bit pointed to by the instruction becomes a set value. If a bit is writable by other bits, however, malfunction occurs. You must not, therefore, access that register using these instructions. Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. 25 To Top / Lineup / Index MB90246A Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source Reset INT9 instruction Exception DTP/external interrupt circuit Channel 0 DTP/external interrupt circuit Channel 1 Input capture (ICU) Channel 0 Input capture (ICU) Channel 1 I/O simple serial interface Channel 2 DTP/external interrupt circuit Channel 2 DTP/external interrupt circuit Channel 3 16-bit free-run timer Overflow Timebase timer Interval interrupt 16-bit re-load timer Channel 0 8-bit PWM timer Channel 0 16-bit re-load timer Channel 1 8-bit PWM timer Channel 1 16-bit re-load timer Channel 2 8-bit PWM timer Channel 2 8/10-bit A/D converter measurement complete 8-bit PWM timer Channel 3 I/O simple serial interface Channel 1 UART transmission complete UART reception complete Delayed interrupt generation module Stack fault : Can be used x : Can not be used : Can be used. With Extended intelligent I/O service (EI2OS) stop function at abnormal operation. : Can be used if interrupt request using ICR are not commonly used. 26 x x x x x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 13 # 15 # 17 # 18 # 19 # 21 # 23 # 25 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 37 # 39 # 42 # 255 08H 09H 0AH 0BH 0DH 0FH 11H 12H 13H 15H 17H 19H 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 25H 27H 2AH FFH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC0H FFFFB8H ICR03 FFFFB4H FFFFB0H FFFFA8H FFFFA0H FFFF98H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF68H FFFF60H FFFF54H FFFC00H ICR12 ICR13 ICR14 ICR15 -- 0000BCH 0000BDH 0000BEH 0000BFH -- Low ICR11*1 0000BBH ICR10*1 0000BAH ICR09*1 0000B9H ICR04 ICR05 ICR06 ICR07 ICR08*1 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B3H Interrupt control register ICR -- -- -- ICR00 ICR01 ICR02 Address -- -- -- 0000B0H 0000B1H 0000B2H Priority*2 High To Top / Lineup / Index MB90246A Series *1: * Interrupt levels for peripherals that commonly use the ICR register are in the same level. * When the extended intelligent I/O service (EI2OS) is specified in a peripheral device commonly using the ICR register, only one of the functions can be used. * When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions, interrupts can not be used on the other function. *2: The level shows priority of same level of interrupt invoked simultaneously. 27 To Top / Lineup / Index MB90246A Series s PERIPHERALS 1. I/O Port (1) Input/output Port Ports 1, 4, 5, 7 to 9, A are general-purpose I/O ports having a combined function as an external bus pin and a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In the external bus mode, the ports are configured as external bus pins, and part of pins for port 4 can be configured as general-purpose I/O port by setting the bus control signal select register (ECSR). * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). * Block diagram PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode N-ch Pin P-ch 28 To Top / Lineup / Index MB90246A Series (2) N-ch Open-drain Port Port 6 is general-purpose I/O port having a combined function as resource input/output. Each pin can be switched between resource and port bitwise. * Operation as output port When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output latch value is set to "0", the output transistor is turned on and the pin status is put into an "L" level output, while writing "1" turns off the transistor and put the pin in a high-impedance status. If the output pin is pulled-up, setting output latch value to "1" puts the pin in the pull-up status. Reading the PDR register returns the pin value (same as the output latch value in the PDR). Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather than the pin value, leaving output latch that is not manipulated unchanged. * Operation as input port Setting corresponding bit of the PDR register to "1" turns off the output transistor and the pin is put into a highimpedance status. Reading the PDR register returns the pin value ("0" or "1"). * Block diagram ADER (analog input enable register) ADER read ADER latch ADER write Internal data bus PDR (port data register) To analog input PDR read RMW (read-modify-write type instruction) Pin Output trigger Output latch PDR write Standby control (SPL=1) Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode 29 To Top / Lineup / Index MB90246A Series (3) Register Configuration Address 000001H bit 15 P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 7 P47 R/W bit 11 P13 R/W bit 6 P46 R/W bit 11 P53 R/W bit 6 P66 R/W bit 11 P73 R/W bit 6 P86 R/W bit 11 P93 R/W bit 6 -- -- bit 11 P13 R/W bit 6 P46 R/W bit 11 P53 R/W bit 6 P66 R/W bit 10 P12 R/W bit 5 P45 R/W bit 10 P52 R/W bit 5 P65 R/W bit 10 P72 R/W bit 5 P85 R/W bit 10 P92 R/W bit 5 PA5 R/W bit 10 P12 R/W bit 5 P45 R/W bit 10 P52 R/W bit 5 P65 R/W bit 9 P11 R/W bit 4 P44 R/W bit 9 P51 R/W bit 4 P64 R/W bit 9 P71 R/W bit 4 P84 R/W bit 9 P91 R/W bit 4 PA4 R/W bit 9 P11 R/W bit 4 P44 R/W bit 9 P51 R/W bit 4 P64 R/W bit 8 P10 R/W bit 3 P43 R/W bit 8 P50 R/W bit 3 P63 R/W bit 8 P70 R/W bit 3 P83 R/W bit 8 P90 R/W bit 3 PA3 R/W bit 8 P10 R/W bit 3 P43 R/W bit 8 P50 R/W bit 3 P63 R/W bit 7 . . . . . . . . . . . . . bit 0 (System reservation area) Port 1 data register (PDR1) Address bit 15. . . . . . . . . . . . bit 8 000004H (PDR5) bit 2 P42 R/W bit 1 P41 R/W bit 0 P40 R/W Port 5 data register (PDR5) bit 0 P60 R/W Port 7 data register (PDR7) bit 0 -- -- Port 9 data register (PDR9) bit 0 PA0 Port A data register (PDRA) Port 8 data register (PDR8) Port 6 data register (PDR6) Port 4 data register (PDR4) Address 000005H bit 15 P57 R/W bit 14 P56 R/W bit 13 P55 R/W bit 12 P54 R/W bit 7 P67 R/W bit 7 . . . . . . . . . . . . . bit 0 (PDR4) Address bit 15. . . . . . . . . . . . bit 8 000006H (PDR7) bit 2 P62 R/W bit 1 P61 R/W Address 000007H bit 15 -- -- bit 14 P76 R/W bit 13 P75 R/W bit 12 P74 R/W bit 7 P87 R/W bit 7 . . . . . . . . . . . . . bit 0 (PDR6) Address bit 15. . . . . . . . . . . . bit 8 000008H (PDR9) bit 2 P82 R/W bit 1 -- -- Address 000009H bit 15 -- R/W bit 14 P96 R/W bit 13 P95 R/W bit 12 P94 R/W bit 7 -- -- bit 7 . . . . . . . . . . . . . bit 0 (PDR8) Address 00000AH bit 15. . . . . . . . . . . . bit 8 (Vacancy) bit 2 PA2 R/W bit 1 PA1 Address 000011H bit 15 P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 7 P47 R/W R/W R/W . . . . . . . . . . . . . bit 0 bit 7 (System reservation area) Port 1 direction register (DDR1) Address bit 15. . . . . . . . . . . . bit 8 000014H (DDR5) bit 2 P42 R/W bit 1 P41 R/W bit 0 P40 R/W Port 5 direction register (DDR5) Port 4 direction register (DDR4) Address 000015H bit 15 P57 R/W bit 14 P56 R/W bit 13 P55 R/W bit 12 P54 R/W bit 7 P67 R/W bit 7 . . . . . . . . . . . . . bit 0 (DDR4) Address bit 15. . . . . . . . . . . . bit 8 000016H (DDR7) bit 2 P62 R/W bit 1 P61 R/W bit 0 P60 R/W Analog input enable register (ADER) (Continued) 30 To Top / Lineup / Index MB90246A Series (Continued) Address 000017H bit 15 -- -- Address 000018H bit 14 P76 R/W bit 13 P75 R/W bit 12 P74 R/W bit 7 P87 R/W Address 000019H bit 15 -- bit 14 P96 bit 13 P95 bit 12 P94 bit 11 P73 R/W bit 6 P86 R/W bit 11 P93 bit 10 P72 R/W bit 5 P85 R/W bit 10 P92 bit 9 P71 R/W bit 4 P84 R/W bit 9 P91 bit 8 P70 R/W bit 3 P83 R/W bit 8 P90 bit 2 P82 R/W bit 1 -- -- bit 0 -- -- Port 9 direction register (DDR9) bit 0 PA0 R/W Port A direction register (DDRA) Port 8 direction register (DDR8) bit 7 . . . . . . . . . . . . . bit 0 (ADER) Port 7 direction register (DDR7) bit 15. . . . . . . . . . . . bit 8 (DDR9) bit 7 . . . . . . . . . . . . . bit 0 (DDR8) Address 00001AH .... ... R/W R/W . R/W . . . .R/W R/W R/W R/W R/W . . . . . . . . . . . . bit 8 bit 7 bit 15 bit 6 bit 5 bit 4 bit 3 bit 2 (Vacancy) -- -- -- -- PA5 R/W PA4 R/W PA3 R/W PA2 R/W bit 1 PA1 R/W R/W : Readble and writable -- : Unused 31 To Top / Lineup / Index MB90246A Series 2. Timebase Timer The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 213/HCLK, 215/HCLK, 217/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC) bit 7 . . . . . . . . . . . . . bit 0 (WDTC) Address 0000A9H bit 15 RESV R/W bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 TBOF R/W bit 10 TBR W bit 9 TBC1 R/W bit 8 TBC0 R/W Initial value 0XX0 0 0 0 0 B R/W: Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit (2) Block Diagram To 8-bit PWM timer Timebase timer counter Divided-by-2 of HCLK x 21 x 22 x 2 3 To watchdog timer ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR : MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) Timebase timer interrupt signal #25(19H)*2 RESV -- -- TBIE TBOF TBR TBC1 TBC0 OF : Overflow HCLK: Oscillation clock *1 : Switch machine clock from oscillation clock to PLL clock *2 : Interrupt signal 32 To Top / Lineup / Index MB90246A Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A8H (TBTC) bit 6 bit 5 bit 4 bit 3 SRST R bit 2 WTE W bit 1 WT1 W bit 0 WT0 W PONR STBR WRST ERST R R R R Initial value XXXXXXXX B R : Read only W: Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 Watchdog timer 2 CLR and start Overflow CLR Watchdog reset generation circuit To internal reset generation circuit Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector CLR 2-bit counter Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 22 ... 4 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK: Oscillation clock 33 To Top / Lineup / Index MB90246A Series 4. 8-bit PWM Timer The 8-bit PWM timer is a re-load timer module that can generate a pulse wave with any period/duty ratio. It uses pulse output control according to timer operation for PWM (Pulse Width Modulation) output. An appropriate external circuit allows the 8-bit PWM timer to operate as a D/A converter. The 8-bit PWM timer module consists of two 8-bit re-load registers used to specify "H" width and "L" width and of a down counter that is loaded alternately with those values and counts down. * A pulse waveform with any period and duty ratio is generated. * An output pulse's duty ratio of 0.4 to 99.6 percent can be set. * An appropriate external circuit allows this PWM timer to operate as a D/A converter. * An interrupt request can be generated by counter underflow. * The count clock can be selected from two types of timebase timer output. (1) Register Configuration * PWM0 to 3 operating mode control register (PWM) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 PWMC0 : 000034H (Vacancy) PWMC1 : 000038H PEN PWMC2 : 00003CH R/W PWMC3 : 00002CH bit 6 PCKS R/W bit 5 POE R/W bit 4 PIE R/W bit 3 PUF R/W bit 2 -- R/W bit 1 -- R/W bit 0 RESV R/W Initial value 0 0 0 0 0XX1 B 0 0 0 0 0XX1 B 0 0 0 0 0XX1 B 0 0 0 0 0XX1 B * PWM0 to 3 re-load register (PRLL, PRLH) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PRLH0 : 000037H PRLH1 : 00003BH PRLH2 : 00003FH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PRLH3 : 00002FH PRLL0 : 000036H PRLL1 : 00003AH PRLL2 : 00003EH PRLL3 : 00002EH Initial value XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B XXXXXXX1 B R/W : Readable and writable -- : Unused X : Indeterminate RESV: Reserved bit 34 To Top / Lineup / Index MB90246A Series (2) Block Diagram Timerbase timer output (22/HCLK) Timerbase timer output (211/HCLK) Pin Count clock selector PWM output latch Reverse Clear Down counter clear Interrupt request #28(1CH) #30(1EH) #32(20H) #34(22H) Output enable P85/PWM0 P86/PWM1 P87/PWM2 P93/INT3/PWM3 Re-load Re-load register L/H selector PWM re-load register (PRLL) Temporary buffer PWM re-load register (PRLH) PEN PCKS POE PIE PUF -- -- RESV PWM operationg mode control register (PWMC) Internal data bus HCLK*: Oscillation clock 35 To Top / Lineup / Index MB90246A Series 5. 16-bit Re-load Timer The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. For this timer, an "underflow" is defined as the timing of transition from the counter value of "0000H" to "FFFFH". According to this definition, an underflow occurs after [re-load register setting value + 1] counts. In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The MB90246A series has 3 channels of 16-bit re-load timers. (1) Register Configuration * Timer control status register 0, 1, 2 upper digits (TMCSR0, TMCSR1, TMCSR2: H) Address TMCSR0 : 000041H TMCSR1 : 000049H TMCSR2 : 000051H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 CSL1 R/W bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (TMCSR : L) Initial value - - - - 0000 B CSL0 MOD2 MOD1 R/W R/W R/W * Timer control status register 0, 1, 2 lower digits (TMCSR0, TMCSR1, TMCSR2: L) Address TMCSR0 : 000040H TMCSR1 : 000048H TMCSR2 : 000050H bit 15. . . . . . . . . . . . .bit 8 bit 7 (TMCSR : H) bit 6 bit 5 bit 4 bit 3 INTE R/W bit 2 UF R/W bit 1 CNTE R/W bit 0 TRG R/W Initial value 00000000 B MOD0 OUTE OUTL RELD R/W R/W R/W R/W * 16-bit timer register 0, 1 (TMR0, TMR1, TMR2) Address TMR0 : 000042H TMR1 : 00004AH TMR2 : 000052H bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D15 D14 D13 D12 D11 D10 D9 R R R R R R R D8 R D7 R D6 R D5 R D4 R D3 R D2 R D1 R D0 R Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB * 16-bit re-load register 0, 1 (TMRL0,TMRL1) Address TMRLR0 : 000044H TMRLR1 : 00004CH TMRLR2 : 000054H bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D15 D14 D13 D12 D11 D10 D9 W W W W W W W D8 W D7 W D6 W D5 W D4 W D3 W D2 W D1 W D0 W Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate 36 To Top / Lineup / Index MB90246A Series (2) Block Diagram Internal data bus TMRLR0*1 16-bit timer register (down counter) UF CLK Count clock generation circuit 3 Gate input Valid clock decision circuit CLK Internal clock Pin Input control circuit External clock P74/TIN0/TOT0 3 Wait signal Prescaler Clear To UART (ch.1)*1 To 8/10-bit A/D converter (ch. 2) Output control circuit Clock selecter Output generation circuit Reverse EN Pin P74/TIN0/TOT0 2 Select signal Operation control circuit Function select -- -- -- -- CSL1CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Interrupt request signal #27 (1BH) <#29 (1DH)>*2 <<#31 (1FH)>> Timer control status register (TMCSR0)*1 37 To Top / Lineup / Index MB90246A Series 6. 16-bit I/O Timer The 16-bit I/O timer module consists of one 16-bit free-run timer, two input capture (ICU) circuits, and four output comparators. This complex module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. Input pulse width and external clock periods can, therfore, be measured. The 16-bit I/O timer consists of: * a 16-bit free-run timer; and * two input captures (ICU). * Block diagram Internal data bus 16-bit free-run timer Dedicated bus Input capture (ICU) 38 To Top / Lineup / Index MB90246A Series (1) 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU). * * * * A counter operation clock can be selected from four internal clocks. An interrupt request can be issued to the CPU by counter overflow. The extended intelligent I/O service (EI2OS) can be activated. The 16-bit free-run timer counter is cleared to "0000H" by a reset or by clearing the timer (TCCS: CLK = 0). * Register configuration * Timer control status register (TCCS) Address 00006EH bit 15. . . . . . . . . . . . .bit 8 bit 7 (Vacancy) RESV R/W bit 6 IVF R/W bit 5 IVFE R/W bit 4 bit 3 bit 2 CLR R/W bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 00000000 B STOP RESV R/W R/W * Timer data register (TCDT) Address 00006DH 00006CH bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T09 T08 T07 T06 T05 T04 T03 T02 T01 T00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable RESV : Reserved bit Initial value 00000000 B 00000000 B * Block diagram Timer data register (TCDT) OF 16-bit free-run timer CLK STOP CLR Count value output to input capture (ICU) Prescaler 2 Timer control status register (TCCS) RESV IVF IVFE STOP RESV CLR CLK1 CLK0 Free-run timer interrupt request #23 (17H)* : Machine clock frequency OF : Overflow * : Interrupt number Internal data bus 39 To Top / Lineup / Index MB90246A Series (2) Input Capture (ICU) The input capture (ICU) consists of a capture register corresponding to two 16-bit external input pins, a control register, and an edge detector. Upon input of a trigger edge through an external input pin, the counter value of the 16-bit free-run timer is stored into the input capture register, and an interrupt request can be generated concurrently. * * * * A capture interrupt can be generated independently for each capture unit. The extended intelligent I/O service (EI2OS) can be activated. A trigger edge direction can be selected from rising/falling/both edges. Since two input capture units can be operated independent of each other, up to two events can be measured independently. * The input capture function is suited for measurements of intervals (frequencies) and pulse-widths. * Register configuration * Input capture control status register (ICS) Address ICS0 : 000064H bit 15. . . . . . . . . . . . .bit 8 (Vacancy) bit 7 ICP1 R/W bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 EG11 R/W bit 2 EG10 R/W bit 1 EG01 R/W bit 0 EG00 R/W Initial value 00000000 B * Input capture register (IPCP0, IPCP1) Address bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IPCP0 : 000061H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 IPCP1 : 000063H IPCP0 : 000060H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IPCP1 : 000062H R/W : Readable and writable R : Read only X : Indeterminate Initial value XXXXXXXXB XXXXXXXXB * Block diagram 16-bit free-run timer Edge detection circuit P71/ASR1 Pin P70/ASR0 Pin Input capture register 0 (IPCP0) Input capture register 1 (IPCP1) Internal data bus Input capture interrupt request (ICU) Input capture control status register(ICS) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 #17 (11H) #15 (OFH) *: Interrupt number 40 To Top / Lineup / Index MB90246A Series 7. Simple I/O Serial Interface The 8/16-bit simple I/O serial interface transfers data synchronously with a clock. * Communications direction: Concurrent processing of transmission (Whether data is to be sent or received must be judged by the user.) * Transfer mode: Clock synchronization function (Only data are transferred.) * Transfer rate: DC to /2 (: Machine clock. Frequencies of up to 8 MHz are available when the machine clock is rated at 16 MHz.) * Shift clock: A machine clock division clock is used as the shift clock. (One of four division ratios can be selected.). A shift clock is output only during data transfer. * Data transfer format: MSB first can be selected. 8 or 16 bits can be selected as data length. Only data are transferred. * Interrupt request: An interrupt request is issued upon termination of transfer. * Inter-CPU connection: Only 1:1 (bidirectional communication) (1) Register Configuration * Serial control status register 1, 2 (SCR) Address SCR0 : 000020H SCR1 : 000024H bit 15. . . . . . . . . . . . .bit 8 (SSR) bit 7 bit 6 bit 5 SOE R/W bit 4 SIE R/W bit 3 SIR R/W bit 2 WBS R/W bit 1 bit 0 Initial value 10000000 B STOP OCKE R/W R/W SMD1 SMD0 R/W R/W * Serial status register 1, 2 (SSR) Address SSR1 : 000021H SSR2 : 000025H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 BUSY R bit 7 . . . . . . . . . . . . . bit 0 (SCR) Initial value - - - - - - - 1B * Serial data register 1, 2 (SDR) Address bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDR1H : 000023H D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 SDR2H : 000027H SDR1L : 000022H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SDR2L : 000026H R/W : Readable and writable R : Read only -- : Unused X : Indeterminate Initial value XXXXXXXXB XXXXXXXXB 41 To Top / Lineup / Index MB90246A Series (2) Block Diagram Serial data register (SDR) Pin PA0/SID1 PA3/SID2 SDRH SDRL Pin PA1/SOD1 PA4/SOD2 Internal data bus Control circuit Shift clock counter Pin PA2/SCK1 PA5/SCK2 2 STOP OCKE SOE SIE SIR WBS SMD1 SMD0 Serial I/O interrupt request #35 (23H)* #18 (12H)* Serial control status register (SCR) -- -- -- -- -- -- -- BUSY Serial status register (SSR) * : Machine clock frequency : Interrupt number 42 To Top / Lineup / Index MB90246A Series 8. UART UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). In addition to the normal duplex communication function (normal mode), UART0 has a master-slave type communication function (multi-processor mode). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: With dedicated baud rate generator, selectable from 12 types External clock input possible Internal clock (A clock supplied from 16-bit re-load timer 2 can be used.) * Data length: 7 bit to 9 bit selective (with a parity bit) 6 bit to 8 bit selective (without a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (not available in multi-processor mode) * Interrupt request: Receive interrupt (receive complete, receive error detection) Receive interrupt (transmit complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) * Master/slave type communication function: 1 (master) to n (slave) communication possible (multi-processor mode) (1) Register Configuration * Status register (USR) Address 000029H bit 15 bit 14 bit 13 PE R bit 12 TDRE R bit 11 RIE R/W bit 10 BCH0 R/W bit 9 RBF R bit 8 bit 7 . . . . . . . . . . . . . bit 0 TBF R (UMC) Initial value 00010000B RDRF OREF R R * Mode control register (UMC) Address 000028H bit 15. . . . . . . . . . . . bit 8 (USR) bit 7 PEN R/W bit 6 SBL R/W bit 11 RC0 R/W bit 5 MC1 R/W bit 10 BCH0 R/W bit 4 MC0 R/W bit 9 P R/W bit 3 SMDE R/W bit 2 RFC W bit 1 SCKE R/W bit 0 SOE R/W Initial value 00000000B Initial value 00000100B * Rate and data register (URD) Address 00002BH bit 15 BCH R/W bit 14 RC3 R/W bit 13 RC2 R/W bit 12 RC1 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 D8 R/W (UIDR/UODR) * Input data register (UIDR) Address 00002AH bit 15 . . . . . bit 9 bit 8 (URD) D8 R bit 7 D7 R bit 7 D7 W bit 6 D6 R bit 6 D6 W bit 5 D5 R bit 5 D5 W bit 4 D4 R bit 4 D4 W bit 3 D3 R bit 3 D3 W bit 2 D2 R bit 2 D2 W bit 1 D1 R bit 1 D1 W bit 0 D0 R bit 0 D0 W Initial value XXXXXXXXB Initial value XXXXXXXXB * Output data register (UODR) Address 00002AH bit 15 . . . . . bit 9 bit 8 (URD) D8 W R/W : Readable and writable R : Read only W : Write only X : Indeterminate 43 To Top / Lineup / Index MB90246A Series (2) Block Diagram Control bus Receive interrupt signal #39 (27H)* Transmit interrupt signal #37 (25H)* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P95/SOD0 Dedicated baud rate generator 16-bit re-load timer 2 Pin P96/SCK0 Clock selector Transmit clock Receive clock Receive control circuit Start bit detection circuit Receive bit counter Receive parity counter Pin P94/SID0 Shift register for reception Reception complete Shift register for transmission UIDR Receive condition decision circuit UODR Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus UMC register PEN SBL MC1 MC0 SMDE RFC SCKE SOE USR register RDRF ORFE PE TDRE RIE TIE RBF TBF URD register BCH RC3 RC2 RC1 RC0 BCH0 P D8 * : Interrupt number 44 To Top / Lineup / Index MB90246A Series 9. DTP/External Interrupt Circuit The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected externally and the F2MC-16F CPU and transmit interrupt requests or data transfer requests generated by peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O service (EI2OS). (1) Register Configuration * DTP/interrupt factor register (EIRR) Address bit 15 bit 14 bit 13 bit 12 RESV -- bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 ER0 R/W (ENIR) 000031H RESV RESV RESV -- -- -- Initial value - - - - 0000 B * DTP/interrupt enable register (ENIR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000030H (EIRR) RESV -- bit 6 bit 5 bit 4 bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W RESV RESV RESV -- -- -- Initial value - - - - 0000 B * Request level setting register (ELVR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000032H (Vacancy) LB3 R/W R/W: Readable and writable -- : Unused RESV : Reserved bit bit 6 LA3 R/W bit 5 LB2 R/W bit 4 LA2 R/W bit 3 LB1 R/W bit 2 LA1 R/W bit 1 LB0 R/W bit 0 LA0 R/W Initial value 00000000 B 45 To Top / Lineup / Index MB90246A Series (2) Block Diagram Request level setting register (ELVR) LB3 LA3 2 Pin P93/INT3/ PWM3 2 Level edge selector 3 Level edge selector 1 LB2 LA2 2 LB1 LA1 LB0 2 LA0 Pin P92/INT2/ATG Level edge selector 2 Level edge selector 0 Internal data bus Pin P91/INT1 Pin P90/INT0 DTP/interrupt factor register (EIRR) RESV RESV RESV RESV ER3 ER2 DTP/external interrupt input detection circuit ER1 ER0 Interrupt request signal #21 (15H)* #19 (13H)* #13 (0DH)* DTP/interrupt enable register (ENIR) RESV RESV RESV RESV EN3 EN2 EN1 EN0 #11 (0BH)* *: Interrupt signal 46 To Top / Lineup / Index MB90246A Series 10. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 R0 R/W (System reservation area) Initial value - - - - - - -0B R/W: Readable and writable -- : Unused (2) Block Diagram Internal data bus -- -- -- -- -- -- -- R0 S factor R latch Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt signal Interrupt request signal #42 (2AH)* 47 To Top / Lineup / Index MB90246A Series 11. 8/10-bit A/D Converter The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * Minimum conversion time: 6.13 s (at machine clock of 16 MHz, including sampling time) * Minimum sampling time: 3.75 s (at machine clock of 16 MHz) * Conversion time: The sampling time can be set arbitrarily. Serial to parallel converter with a sample hold circuit * Conversion method * Resolution: 10-bit or 8-bit selective * Analog input pins: Selectable from eight channels by software Single conversion mode: Single conversion for the specified channel Scan conversion mode: Scan conversions for maximum of four channel * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. * Starting factors for conversion: Selected from software activation, 16-bit re-load timer 1 output (rising edge), and external trigger (falling edge). * A data buffer that covers four channels is supported. The results of conversion are stored into the data buffer. 48 To Top / Lineup / Index MB90246A Series (1) Register Configuration * A/D control status register upper digits (ADCSH) Address 000071H bit 15 -- -- bit 14 ACS2 R/W bit 13 ACS1 R/W bit 12 ACS0 R/W bit 11 -- -- bit 10 -- -- bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (ADCSL) CREG SCAN R/W R/W Initial value - 000 - - 00 B * A/D control status register lower digits (ADCSL) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000070H (ADCSH) BUSY R/W bit 6 INT R/W bit 5 INTE R/W bit 4 -- -- bit 3 STS1 R/W bit 2 STS0 R/W bit 1 bit 0 STAR RESV R/W R/W Initial value 000 - 0000 B * A/D data register 0 to 3 (ADTH, ADTL) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ADTH0 : 000075H ---- -- D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ------ ADTH1 : 000077H ADTH2 : 000079H R R R R R R R R R R R R R R * * ADTH3 : 00007BH ADTL0 : 000074H ADTL1 : 000076H ADTL2 : 000078H ADTL3 : 00007AH Initial value - - - - - - **B XXXXXXXX B * Conversion time setting register (ADCT) Address 000073H 000072H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B XXXXXXXX B * Analog input enable register (ADER) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000016H (DDR7) ADE7 R/W bit 6 bit 5 bit 4 ADE4 R/W bit 3 ADE3 R/W bit 2 ADE2 R/W bit 1 ADE1 R/W bit 0 ADE0 R/W ADE6 ADE5 R/W R/W Initial value 11111111 B R/W: Readable and writable R : Read only -- : Unused X : Indeterminate * : The CREG bit value of ADCSH makes different storage styles. RESV : Reserved bit 49 To Top / Lineup / Index MB90246A Series (2) Block Diagram Conversion time setting register (ADCT) SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20 4 4 4 4 Register selection A/D data register 0 to 3 ADTH0 to ADTH3, ADTL0 to ADTL3 AVRH AVRL AVCC AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 Analog channel selector Sample hold circuit A/D converter TO P92/INT2/ATG Clock selector Control circuit 2 3 -- ACS2 ACS1 ACS0 -- -- CREG SCAN BUSY INT INTE -- STS1 STS0 STAR RESV A/D control status register (ADCS) : Machine clock frequency TO : 16-bit re-load timer channel 1 output Interrupt request #33 (21H) 50 Internal data bus To Top / Lineup / Index MB90246A Series 12. 8-bit D/A Converter The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A control register 0 (DACR0) Address 00005BH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 DAE0 R/W bit 7 . . . . . . . . . . . . . bit 0 (DADR0) Initial value - - - - - - -0B * D/A control register 1 (DACR1) Address 00005DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 DAE1 R/W bit 7 . . . . . . . . . . . . . bit 0 (DADR1) Initial value - - - - - - -0B * D/A control register 2 (DACR2) Address 00005FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 DAE2 R/W bit 7 . . . . . . . . . . . . . bit 0 (DADR2) Initial value - - - - - - -0B * D/A data register 0 (DADR0) Address 00005AH bit 15 . . . . . . . . . . . . bit 8 bit 7 (DACR0) DA07 R/W bit 6 DA06 R/W bit 5 DA05 R/W bit 4 DA04 R/W bit 3 DA03 R/W bit 2 DA02 R/W bit 1 DA01 R/W bit 0 DA00 R/W Initial value XXXXXXXX B * D/A data register 1 (DADR1) Address 00005CH bit 15 . . . . . . . . . . . . bit 8 bit 7 (DACR1) DA17 R/W bit 6 DA16 R/W bit 5 DA15 R/W bit 4 DA14 R/W bit 3 DA13 R/W bit 2 DA12 R/W bit 1 DA11 R/W bit 0 DA10 R/W Initial value XXXXXXXX B * D/A data register 2 (DADR2) Address 00005EH bit 15 . . . . . . . . . . . . bit 8 bit 7 (DACR2) DA27 R/W R/W : Readable and writable -- : Unused X : Indeterminate bit 6 DA26 R/W bit 5 DA25 R/W bit 4 DA24 R/W bit 3 DA23 R/W bit 2 DA22 R/W bit 1 DA21 R/W bit 0 DA20 R/W Initial value XXXXXXXX B 51 To Top / Lineup / Index MB90246A Series (2) Block Diagram Internal data bus D/A data register (DADR0) DAx7 DAx6 DAx5 DAx4 DAx3 DAx2 DAx1 DAx0 D/A converter DVRH DAx7 Pin 2R DAx6 2R DAx5 2R DAx4 2R DAx3 2R DAx2 2R DAx1 2R DAx0 2R R P82/DAO0 R R R R R R R DVRL Standby control D/A control register (DACR0) Internal data bus Note: The 8-bit D/A converter supports channels 0 to 2. A value enclosed by < and > is for channels 1 and 2. 52 To Top / Lineup / Index MB90246A Series 13. DSP Interface for the IIR Filter The DSP interface for the IIR filter is a unit which covers product addition (Bi x Yj + Am x Xn) by hardware. This interface allows IIR filter calculation to be performed readily and in a high speed. The DSP interface for the IIR filter has the following features. * * * * Coefficients A and B, and variables X and Y have 16-bit length, and four banks are supported. (1 to 4) + (1 to 4) product terms can be selected. Data can be rounded and clipped in units of 10 or 12 bits. With two or more concatenated banks used, the results of an operation can be transferred to the subsequent bank register. * Operation time: ((M + N + 1) x B + 1)/ s(M, N = number of product terms, B = number of banks, : machine clock) (1) Register Configuration * Product addition control status register upper digits (MCSR:H) Address 000081H bit 15 -- -- bit 14 WEY R/W bit 13 bit 12 bit 11 N1 R/W bit 10 N0 R/W bit 9 M1 R/W bit 8 M0 R/W bit 7 . . . . . . . . . . . . . bit 0 (MCSR:L) Initial value - XXXXXXX B WENY WENX R/W R/W * Product addition control status register lower digits (MCSR:L) Address 000080H bit 15 . . . . . . . . . . . . bit 8 bit 7 (MCSR:H) RND R/W bit 6 CLP R/W bit 5 DIV R/W bit 4 BF R bit 3 BNK1 R/W bit 2 BNK0 R/W bit 1 TRG W bit 0 MAE R/W Initial value XXX0XXX0 B * Product addition control register upper digits (MCCR:H) Address 000083H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 RESV R/W bit 8 RESV R/W bit 7 . . . . . . . . . . . . . bit 0 (MCCR:L) Initial value - - - - - - 00 B * Product addition control register lower digits (MCCR:L) Address 000082H bit 15 . . . . . . . . . . . . bit 8 bit 7 (MCCR:H) OVF R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CNTD CNTC CNTB CDRD CDRC CDRB CDRA R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B * Product addition output register (MDORL, M, H) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MDORH : 000088H S R S R S R S R S R D34 D33 D32 R R R Initial value XXXXXXXX B MDORM : 000086H D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 XXXXXXXX XXXXXXXX B R R R R R R R R D8 R R D7 R R D6 R R D5 R R D4 R R D3 R R D2 R R D1 R R D0 R XXXXXXXX XXXXXXXX B MDORL : 000084H D15 D14 D13 D12 D11 D10 D9 R R R R R R R R/W: Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit 53 To Top / Lineup / Index MB90246A Series (2) Block Diagram Internal data bus Transfer data selector Transfer data selector Coefficient register A0 to A3 Coefficient register B0 to B3 Input data register X0 to X3 Input data register Y0 to Y3 Bank selection Register selection Coefficient register selector Register selection Register selection Input data selector Product addition unit Bank/register selector Product adder 4 Right shift and clip 3 OVF CNTD CNTC CNTB CDRD CDRC CDRB CDRA Product addition control register (MCCR) Product addition output register L (MDORL) Product addition output register M (MDORM) Product addition output register H (MDORH) 2 3 -- 4 WEY WENY WENX N1 N0 M1 M0 RND CLP DIV BF BNK1 BNK0 TRG MAE Product addition control status register (MCSR) 54 To Top / Lineup / Index MB90246A Series 14. Low-power Consumption (Stand-by) Mode The F2MC-16F has the following CPU operating mode configured by selection of an clock operation control. * Stand-by mode The hardware stand-by mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit, and stopping oscillation clock (stop mode, hardware standby mode). Gear function contributes to the low-power dissipation by providing options of divide-by-2, 4, or 16 external clock frequencies, whichiare usually derived from non-divided frequencies. (1) Register Configuration * Standby control register (STBYC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A0H (Vacancy) STP W bit 6 SLP W bit 5 SPL R/W bit 4 RST R/W bit 3 bit 2 bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 0 0 0 1XXXX B OSC1 OSC0 R/W R/W R/W : Readable and writable W : Write only X : Indeterminate 55 To Top / Lineup / Index MB90246A Series (2) Block Diagram Low-power consumption mode control register (STBYC) STP SLP SPL RST OSC1 OSC0 CLK1 CLK0 Pin high-impedance control circuit Internal reset generation circuit Pin Hi-z control RST Pin Internal reset CPU clock control circuit Cancellation of reset 2 RST Standby control circuit CPU clock Stop and sleep signal Cancellation of interrupt HST Pin Stop signal Machine clock Peripheral clock control circuit Peripheral clock Clock generation block Clock selector Cancellation of oscillation stabilization time 2 2 Oscillation stabilization time selector Divided -by-2 System clock generation circuit X0 Pin Divided -by-2 Divided -by-4 Main clock Divided -by-214 Divided -by-2 Divided -by-2 Divided -by-2 Timebase timer DDC Oscillation clock X0 Pin DDC: Direct duty control 56 To Top / Lineup / Index MB90246A Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVRH, DVRL Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature VI VO IOL IOLAV IOLAV IOH IOHAV IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -30 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 10 4 50 -10 -4 -48 600 +70 +150 Unit V V V V V V mA mA mA mA mA mA mW C C *1 *1 *1 *2 *2 *3 *4 *5 *3 *4 *5 Remarks *1: AVCC, AVRH, AVRL, DVRH and DVRL shall never exceed VCC. DVRL shall never exceed DVRH. AVRL shall never exceed AVRH. *2: VI and VO shall never exceed VCC + 0.3 V. *3: The maximum output current is a peak value for a corresponding pin. *4: Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: Total average current is an average current value observed for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 57 To Top / Lineup / Index MB90246A Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage Operating temperature VCC TA Value Min. 4.5 2.0 -30 Max. 5.5 5.5 +70 Unit V V C Remarks Normal operation Retains RAM data at the time of operation stop External bus mode WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 58 To Top / Lineup / Index MB90246A Series 3. DC Characteristics (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Typ. Max. -- VCC = 5.0 V 10% 0.7 VCC 2.2 0.8 VCC -- VCC - 0.3 VCC - 0.3 VCC = 5.0 V 10% -- VCC - 0.3 VCC - 0.3 VCC - 0.3 VCC - 0.5 -- -- -- -- -- -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.8 0.2 VCC VCC + 0.3 -- V V V V V V V V V Parameter Symbol VIH "H" level input voltage VIH2 VIH1S VIHM VIL1 "L" level input voltage VIL2 VIL1S VILM "H" level output voltage "L" level output voltage VOH Pin name CMOS input pin TTL input pin Hysteresis input pin MD0 to MD2 CMOS input pin TTL input pin Hysteresis input pin MD0 to MD2 All ports other VCC = 4.5 V than P60 to P67 IOH = -4.0 mA All output pins VCC = 4.5 V IOL = 4.0 mA VOL -- -- 0.4 V Open-drain output ILEAK leakage current IIH1 "H" level input current IIH2 IIH3 IIL1 "L" level input current IIL2 IIL3 Pull-up resistance R P60 to P67 CMOS input pins other than RST TTL input pin -- -- 0.1 10 A VCC = 5.5 V VIH = 0.7 VCC VCC = 5.5 V VIH = 2.2 VCC -- -- -- -- -- -- 22 -- -- -- -- -- -- -- -10 -10 -10 10 10 10 110 A A A A A A k Hysteresis input VCC = 5.5 V pin VIH = 0.8 VCC CMOS input pins other than RST TTL input pin VCC = 5.5 V VIL = 0.3 VCC VCC = 5.5 V VIL = 0.8 V Hysteresis input VCC = 5.5 V pin VIL = 0.2 VCC RST -- (Continued) 59 To Top / Lineup / Index MB90246A Series (Continued) (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Typ. Max. Internal operation at 16 MHz VCC = 5.0 V 10% Normal operation -- Internal operation at 16 MHz VCC = 5.0 V 10% In sleep mode TA = +25C VCC = 4.5 V to 5.5 V In stop mode and hardware standby mode -- -- 80 100 mA Parameter Symbol Pin name ICC VCC Power supply current ICCS -- 30 50 mA ICCH -- -- 0.1 10 A Input CIN capacitance Other than AVCC, AVSS, VCC, VSS -- 10 -- pF 60 To Top / Lineup / Index MB90246A Series 4. AC Characteristics (1) Reset, Hardware Standby Input Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRSTL tHSTL RST HST -- 5 tCYC* 5 tCYC* -- -- ns ns Parameter Reset input time Hardware standby input time * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." Note: Upon hardware standby input, divide-by-32 is selected as the machine cycle. tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC ratings Pin CL CL is a load capacitance connected to a pin under test. Capacitors of CL = 30 pF should be connected to CLK pin, while CL of 80 pF is connected to address bus (A23 to A00) and data bus (D15 to D00), RD, WRH and WRL pins. 61 To Top / Lineup / Index MB90246A Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Unit Remarks Min. Max. -- 30 ms * Due to repeated 1 -- ms operations Parameter Power supply rising time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC VCC -- * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * When HST is set to "L", apply power according to this table to cause a power-on reset irrespective of whether or not a power-on reset is required. * For built-in resources in the device, re-apply power to the resources to cause a power-on reset. tR VCC 4.5 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. 0.2 V Main power supply voltage VCC Sub power supply voltage VSS RAM data retained It is recommended to keep the rising speed of the supply voltage at 50 mV/ms. 62 To Top / Lineup / Index MB90246A Series (3) Clock Timings * Operation at 5.0 V 10% Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/ falling time Symbol Pin name FC tC PWH, PWL tCR, tCF X0, X1 X0, X1 X0 X0 Condition VCC = 5.0 V 10% -- (AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Unit Remarks Min. Typ. Max. 16 -- 32 MHz 1/Fc -- -- ns Recommended 10 -- -- ns duty ratio of 30% to 70% Maximum value -- -- 11 ns = tCR + tCF VCC = 5.0 V 10% * Clock timings tC 0.7 VCC 0.7 VCC 0.3 VCC PWH tCF PWL tCR 0.7 VCC 0.3 VCC * Relationship between clock frequency and power supply voltage (V) Power supply voltage VCC 5.5 Normal operation range (TA = -30C to +70C) 4.5 0 16 Clock frequency FC 32 (MHz) 63 To Top / Lineup / Index MB90246A Series (4) Clock Output Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. CLK CLK -- 2 tC*1 32tC*1*2 ns ns Parameter Cycle time (machine cycle) CLK CLK Symbol tCYC tCHCL VCC = 5.0 V 10% 1 tCYC/2 - 20 1 tCYC/2 + 20 *1: For tC (clock cycle time), refer to "(3) Clock Timings." *2: This case is applied when the lowest speed (1/16) is selected by the clock gear function with the clock frequency (FC) set at 16 MHz. tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V 64 To Top / Lineup / Index MB90246A Series (3) Bus Read Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. A00 to A23 VCC = 5.0 V 10% tAVDV tRLRH D15 to D00 RD D15 to D00 D15 to D00 A00 to A23 CLK, A00 to A23 RD, CLK -- 1 tCYC*/2 - 25 1 tCYC*/2 - 25 -- -- ns ns -- VCC = 5.0 V 10% -- (N + 1) x 1 tCYC** - 25 -- 0 1 tCYC*/2 - 20 1 tCYC*/2 - 20 -- (N + 1.5) x 1 tCYC* - 40 -- (N + 1) x 1 tCYC** - 30 -- -- ns ns ns ns ns ns Parameter Effective address RD time Effective address effective data input RD pulse width Symbol tAVRL RD effective data tRLDV input RD data hold time tRHDX RD address effective time Effective address CLK time RD CLK time tRHAX tAVCH tRLCL N: Stands for the number of wait cycles. With no wait, N is set at "0". (The number of wait cycles depends on an automatic wait and external RDY.) * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." tAVCH CLK 0.8 V tAVRL RD tRLCL 2.4 V 0.8 V tRLRH 0.8 V 2.4 V tRHAX A00 to A23 2.4 V 0.8 V 2.4 V 0.8 V tRLDV tAVDV D00 to D15 2.2 V 0.8 V tRHDX 2.2 V 0.8 V 65 To Top / Lineup / Index MB90246A Series (4) Bus Write Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Unit Remarks Pin name Condition Min. Max. A00 to A23 WRL, WRH D15 to D00 D15 to D00 A00 to A23 -- WRL, CLK VCC = 5.0 V 10% VCC = 5.0 V 10% 1 tCYC*/ 2 - 20 (N + 1) x 1 tCYC** - 25 (N + 1) x 1 tCYC** - 40 1 tCYC*/ 2 - 20 1 tCYC*/ 2 - 20 1 tCYC*/ 2 - 25 -- -- -- -- -- -- ns ns ns ns ns ns Parameter Effective address WRL, WRH time Symbol tAVWL WRL, WRH pulse width tWLWH Write data WRL, WRH time WRL, WRH data hold time WRL, WRH address effective time tDVWH tWHDX tWHAX WRL, WRH CLK tWLCL time N: Stands for the number of wait cycles. With no wait, N is set at "0". (The number of wait cycles depends on an automatic wait and external RDY.) * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." tWLCL 0.8 V CLK tAVWL WRL, WRH 0.8 V tWLWH 2.4 V tWHAX A00 to A23 2.4 V 0.8 V tDVWH D00 to D15 2.4 V 0.2 V Write data 2.4 V 0.8 V tWHDX 2.4 V 0.2 V 66 To Top / Lineup / Index MB90246A Series (5) Ready Input Timing * CLK signal standards (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. RD/WRH/ WRL, RDY RDY RDY VCC = 5.0 V 10% -- 0 30 0 N x1 tCYC* + 15 -- -- ns ns ns Parameter RD/WRH/WRL RDY time RDY setup time (in diallocating) RDY hold time Symbol tRYHS tRHDV tRYHH N: Stands for the number of wait cycles. With no wait, N is set at "0". (The number of wait cycles depends on an automatic wait and external RDY.) * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. * Ready input timing (CLK signal standards) CLK A00 to A23 RD/WRH/WRL 0.8 V tRYH RDY (wait not inserted) 2.2 V tRYHH 2.2 V RDY (wait inserted) 0.8 V 0.8 V 2.2 V 2.2 V tRHDV tRYHH 67 To Top / Lineup / Index MB90246A Series * RD/WRH/WRL signal standards (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. RD/WRH/ WRL, RDY RDY RD/WRH/ WRL, RDY -- VCC = 5.0 V 10% -- 0 1/2 tCYC*3 + 20 1 tCYC*3 - 15 N x1 tCYC*3 + 15*1 (m + 1) x 1 tCYC*2,*3 2 tCYC*3 - 25 ns ns ns Parameter RD/WRH/WRL RDY time RDY pulse width RDY RD Symbol tRYHS tRYPW tRHDV N: Stands for the number of wait cycles. With no wait, N is set at "0". (The number of wait cycles depends on an automatic wait and external RDY.) m: Stands for the number of RDY wait cycles. With no wait, m is set at "0". *1: Use the automatic ready function when the setup time is not sufficient. *2: If the pulse width has exceeded the maximum value, the wait period may be extended beyond the specified number of cycles by one cycle. *3: For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." * Ready input timing (RD/WRH/WRL signal standards) A00 to A23 RD/WRH/WRL 0.8 V 2.4 V tRYHS RDY (wait not inserted) 2.2 V tRYPW 2.2 V RDY (wait inserted) 0.8 V 0.8 V 2.2 V tRHDV 68 To Top / Lineup / Index MB90246A Series (8) Hold Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. HAK HAK VCC = 5.0 V 10% -- 30 1 tCYC* 1 tCYC* 2 tCYC* ns ns Parameter Symbol Pins in floating status tXHAL HAK time HAK pin valid time tHAHV * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HRQ HAK 0.8 V tXHAL Pins High impedance 2.4 V tHAHV (9) UART Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Symbol Pin name Condition Unit Remarks Min. Max. tSCYC tSLOV tIVSH SCK0 SCK0, SOD0 SCK0, SID0 SCK0, SID0 SCK0 -- tSLSH tSLOV tIVSH SCK0 SCK0, SID0 -- SCK0, SID0 VCC = 5.0 V 10% 4 tCYC* -- 60 60 -- 150 -- -- ns ns ns ns External shift clock mode CL = 80 pF for an output pin VCC = 5.0 V 10% -- 8 tCYC* -80 100 60 4 tCYC* -- 80 -- -- -- ns ns ns ns ns Internal shift clock mode CL = 80 pF for an output pin Parameter Serial clock cycle time SCK SOD delay time Valid SID SCK SCK valid SID hold tSHIX time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOD delay time Valid SID SCK tSHSL SCK valid SID hold tSHIX time * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor value connected to pins while testing. 69 To Top / Lineup / Index MB90246A Series * Internal shift clock mode SCK0 0.8 V tSLOV SOD0 2.4 V 0.8 V tSCYC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SID0 * External shift clock mode SCK0 0.2 VCC tSLOV SOD0 tSLSH 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SID0 70 To Top / Lineup / Index MB90246A Series (10) Timer Input Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Symbol Pin name Condition Unit Remarks Min. Max. ASR0, ASR1, tTIWH, -- ns -- 4 tCYC* tTIWL TIN0 to TIN2 Parameter Input pulse width * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." 0.8 VCC ASR0, ASR1 TIN0 to TIN2 tTIWH 0.8 VCC 0.2 VCC 0.2 VCC tTIWL (11) Timer Output Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Symbol Pin name Condition Unit Remarks Min. Max. TOT0 to TOT2, tTO PWM0 to VCC = 5.0 V 10% -- 40 ns PWM3 Parameter CLK TOT transition time 2.4 V CLK TOT 2.4 V 0.8 V tTO 71 To Top / Lineup / Index MB90246A Series (12) I/O Simple Serial Timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. SCK1, SCK2 SCK1, SOD1, SCK2, SOD2, SCK1, SID1, SCK2, SID2, SCK1, SID1, SCK2, SID2, -- 2 tCYC* -- 1 tCYC* 1 tCYC* -- 1 tCYC*/2 -- -- ns ns ns ns Internal shift clock mode CL = 80 pF for an output pin Parameter Serial clock cycle time SCK SOD delay time Valid SID SCK Symbol tSCYC tSLOV tIVSH SCK valid SID hold tSHIX time * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." Note: CL is the load capacitor value connected to pins while testing. * Internal shift clock mode tSCYC SCK1, SCK2 0.8 V tSLOV SOD1, SOD2 2.4 V 0.8 V tIVSH SID1, SID2 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 2.4 V 0.8 V 72 To Top / Lineup / Index MB90246A Series (13) Trigger input timing (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Remarks Min. Max. ATG, INT0 to INT3 -- 5 tCYC* -- ns Parameter Input pulse width Symbol tTRGH, tTRGL * : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing." 0.8 VCC ATG INT0 to INT3 tTRGH 0.8 VCC 0.2 VCC 0.2 VCC tTRGL 73 To Top / Lineup / Index MB90246A Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Min. Typ. Max. -- -- 8, 10 10 bit -- -- -- 3.0 LSB -- -- -- 2.0 LSB -- -- -- 1.9 LSB -- AN0 to AN7 AN0 to AN7 -- -- -- -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL -- Supply current when the CPU stops AVCC (AVCC = 5.5 V) AVRH -- Supply current when AVRH the CPU stops (AVCC = 5.5 V) AN0 to AN7 -- AVCC -- Use the A/D data register for setup. VCC = 5.0 V 10% AVRL AVRL AVRL - 1.0 LSB + 1.0 LSB + 3.0 LSB AVRH AVRH AVRH - 4.0 LSB - 1.0 LSB + 1.0 LSB Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Symbol -- -- -- -- VOT mV mV s ns ns ns ns A V V V mA A A A LSB Full-scale transition VFST voltage -- Conversion time*1 Sampling -- period Conversion -- period a Conversion -- period b Conversion -- period c Analog port input current IAIN Analog input voltage VAIN -- Reference voltage -- IA Power supply current IAS*2 1.25 560 125 125 250 -- AVRL AVRL + 2.7 0 -- -- -- -- -- -- -- -- -- -- 0.1 -- -- -- 15 -- 0.7 -- -- -- -- -- -- -- 3 AVRH AVCC AVRH - 2.7 20 5 2 5 4 AVRH - AVRL 2.7 IR Reference voltage supply current IRS*2 Offset between channels -- *1: Glossary for conversion time Conversion time 1 tCYC* Sampling period Conversion period a Conversion period b Conversion period c 2 tCYC* A/D activation ADCS bit 1: Sets STAR End of conversion ADCS bit 6: INT "H" (Interrupt occurred to CPU) * : For tCYC, see s Electrical Characteristics, 4, "AC Characteristics," Cycle time (machine cycle) in paragraph (4), "Clock output timing." *2: IAS and IRS signify currents when the A/D converter does not operate and when the CPU is out of service, respectively. 74 To Top / Lineup / Index MB90246A Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter With 10 bits supported, an analog voltage can be divided into 210 parts. Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, linearity error, differential linearity error and error caused by noise. Digital output 11 1111 1111 11 1111 1110 * * * * * * * * * * * (1 LSB x N + VOT) Linearity error 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T VFST 1 LSB = VFST - VOT 1022 VNT - (1 LSB x N + VOT) [LSB] 1 LSB V( N+1 )T - VNT - 1 LSB [LSB] 1 LSB Linearity error = Differential linearity error = 75 To Top / Lineup / Index MB90246A Series 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 300 or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling time = 0.56 s @machine clock of 16 MHz). * Block diagram of analog input circuit model Analog input pin C0 Comparator RON1 RON2 Comparator RON1: Approx. 300 RON2: Approx. 150 C0: Approx. 60 pF C1: Approx. 4 pF C1 Comparator Note: Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 8. 8-bit D/A Converter Electrical Characteristics (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -30C to +70C) Value Pin name Condition Unit Min. Typ. Max. -- -- 8 8 bit -- -- -- -- 0.9 LSB VCC = DVRH = 5.0 V, -- -- -- 1.2 % DVRL = 0.0 V -- -- 10 20 s Load capacitance: 20 pF -- VCC V DVRH VSS + 2.0 2.0 V -- VCC - 2.0 V DVRL VSS DVRH - DVRL DVRH During conversion -- 1.0 1.5 mA When the CPU is DVRH -- -- 10 A stopped -- -- -- 28 -- k Parameter Resolution Differential linearity error Absolute accuracy Conversion time Analog power supply voltage Reference voltage supply current Analog output impedance Symbol -- -- -- -- -- -- ID IDH -- 76 To Top / Lineup / Index MB90246A Series s EXAMPLE CHARACTERISTICS (1) "H" Level Output Voltage (2) "L" Level Output Voltage VCC - VOH 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 -2 VOH - IOH TA = +25C VOL (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 VOL - IOL TA = +25C VCC = 5.0 V VCC = 5.0 V -4 -6 -8 IOH (mA) 4 6 8 IOL (mA) (3) Power Supply Current ICC (mA) 80 70 ICC - VCC Internal operating frequency 16 MHz ICCS (mA) 25 ICCS - VCC Internal operating frequency 16 MHz 20 60 50 40 30 4 MHz 13 MHz 13 MHz 10 MHz 8 MHz 15 10 MHz 8 MHz 10 20 2 MHz 5 4 MHz 10 2 MHz 0 4.0 4.5 5.0 5.5 6.0 VCC (V) 0 4.0 4.5 5.0 5.5 6.0 VCC (V) 77 To Top / Lineup / Index MB90246A Series s INSTRUCTIONS (421 INSTRUCTIONS) Table 1 Item Mnemonic Description of Items in Instruction List Description English upper case and symbol: Described directly in assembler code. English lower case: Converted in assembler code. Number of letters after English lower case: Describes bit width in code. Describes number of bytes. Describes number of cycles. For other letters in other items, refer to table 4. Describes correction value for calculating number of actual states. Number of actual states is calculated by adding value in the ~section. Describes operation of instructions. Describes a special operation to 15 bits to 08 bits of the accumulator. Z : Transfer 0. X : Sign-extend and transfer. - : No transmission Describes a special operation to the upper 16-bit of the accumulator. * : Transmit from AL to AH. - : No transfer. Z : Transfer 00H to AH. X : Sign-extend AL and transfer 00H or FFH to AH. Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry) flags. * : Changes after execution of instruction. - : No changes. S : Set after execution of instruction. R : Reset after execution of instruction. # ~ B Operation LH AH I S T N Z V C RMW Describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : Read-modify-write instruction - : Not read-modify-write instruction Note: Not used to addresses having different functions for reading and writing operations. 78 To Top / Lineup / Index MB90246A Series Table 2 Item A Description of Symbols in Instruction Table Description 32-bit accumlator The bit length is dependent on the instructions to be used. Byte : Lower 8-bit of AL Word :16-bit of AL Long : AL: 32-bit of AH Upper 16-bit of A Lower 16-bit of A Stack pointer (USP or SSP) Program counter Stack pointer upper limited register Stack pointer lower limited register Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB DTB, ADB, SSB, USB, DPR R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Specify shortened direct address. Specify direct address. Specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value Vector number (0 to 15) Vector number (0 to 255) AH AL SP PC SPCU SPCL PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 (Continued) 79 To Top / Lineup / Index MB90246A Series (Continued) Item ( )b rel ear eam rlst Bit address Specify PC relative branch. Specify effective address (code 00 to 07). Specify effective address (code 08 to 1F). Register allocation Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Symbol RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Field Address type Register direct "ea" corresponds to byte, word, and long word from left respectively. -- Number of bytes in address extension block* Description Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 0 0 2 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address Note: Number of bytes for address extension corresponds to "+" in the # (number of bytes) part in the instruction table. 80 To Top / Lineup / Index MB90246A Series Table 4 Code Number of Execution Cycles in Addressing Modes Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 (a)* Number of execution cycles for addressing modes Listed in instruction table 1 4 1 1 2 2 2 1 00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table. Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles Operand Internal register Internal RAM even address Internal RAM odd address Other than internal RAM even address Other than internal RAM odd address External data bus 8-bit (b)* byte +0 +0 +0 +1 +1 +1 (c)* word +0 +0 +1 +1 +3 +3 (d)* long +0 +0 +2 +2 +6 +6 Notes: * (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table. 81 To Top / Lineup / Index MB90246A Series Table 6 Mnemonic MOV A, dir MOV A, addr16 MOV A, Ri MOV A, ear MOV A, eam MOV A, io MOV A, #imm8 MOV A, @A MOV A, @RLi + disp8 MOV A, @SP + disp8 MOVP A, addr24 MOVP A, @A MOVN A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RWi + disp8 A, @RLi + disp8 A, @SP + disp8 MOVPX A, addr24 MOVPX A, @A MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH dir, A addr16, A Ri, A ear, A eam, A io, A @RLi + disp8, A @SP + disp8, A addr24, A Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH A, ear A, eam Ri, ear Ri, eam MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX Transmission Instruction (Byte) [50 Instructions] B (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) LH AH # ~ 2 2 2 3 1 1 1 2 2 + 2 + (a) 2 2 2 2 2 2 6 3 3 3 3 5 2 2 1 1 2 2 2 3 1 2 1 2 2 + 2 + (a) 2 2 2 2 2 2 3 2 6 3 3 3 3 5 2 2 2 2 2 3 1 1 2 2 2 + 2 + (a) 2 2 6 3 3 3 3 5 2 2 2 + 3 + (a) 3 2 3 2 2 + 3 + (a) 2 2 3 3 3 3 2 3 3 + 2 + (a) 2 2 byte (A) ((RLi) + disp8) byte (A) ((SP) + disp8) byte (A) (addr24) byte (A) ((A)) byte (A) imm4 Z Z Z Z Z Z Z Z Z Z Z Z Z * * * * * * * - * * * - * * * * * * * * - * * * * - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - X X X X X X X X byte (A) ((RWi) + disp8) X byte (A) ((RLi) + disp8) X byte (A) ((SP) + disp8) X X byte (A) (addr24) X byte (A) ((A)) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) - - - - - - - - - - - - - - - - - - - - Z Z - - byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte ((RLi) + disp8) (A) byte ((SP) + disp8) (A) byte (addr24) (A) byte (Ri) (ear) byte (Ri) (eam) byte ((A)) (Ri) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) 0 3 2 2 + 3 + (a) 2 x (b) 0 4 2 2 + 5 + (a) 2 x (b) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 82 To Top / Lineup / Index MB90246A Series Table 7 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW # Transmission Instruction (Word) [40 Instructions] ~ B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 A, dir 2 2 A, addr16 3 2 A, SP 1 1 A, RWi 1 1 A, ear 2 A, eam 2 + 2 + (a) 2 A, io 2 2 A, @A 2 2 A, #imm16 3 3 A, @RWi + disp8 2 6 A, @RLi + disp8 3 3 A, @SP + disp8 3 3 5 MOVPW A, addr24 2 2 MOVPW A, @A MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVPW MOVPW - - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (A) ((SP) + disp8) - - word (A) (addr24) - word (A) ((A)) word (dir) (A) word (addr16) (A) word (SP) imm16 word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word ((SP) + disp8) (A) - - word (addr24) (A) - word ((A)) (RWi) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) - - - - - * * * * * * * - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW dir, A addr16, A SP #imm16 , SP A , RWi, A ear, A eam, A io, A @RWi + disp8, A @RLi + disp8, A @SP + disp8, A addr24, A @A, RWi RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2 2 2 1 2 2 + (a) 2 3 6 3 3 3 2 3 + (a) 3 3 + (a) 2 3 2 2 + (a) 2 MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 0 3 2 2 + 3 + (a) 2 x (c) 0 4 2 2 + 5 + (a) 2 x (c) Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 83 To Top / Lineup / Index MB90246A Series Table 8 Mnemonic MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL A, @SP + disp8 MOVPL A, addr24 MOVPL A, @A MOVPL @A, RLi MOVL MOVPL MOVL MOVL @SP + disp8, A addr24, A ear, A eam, A Transmission Instruction (Long) [11 Instructions] B 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) Operation long (A) (ear) long (A) (eam) long (A) imm32 long (A) ((SP) + disp8) LH AH # ~ 2 2 2 + 3 + (a) 5 3 3 4 5 4 2 3 2 5 long (A) (addr24) long (A) ((A)) long ((A)) (RLi) long ((SP) + disp8) (A) - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - 3 4 5 4 2 2 2 + 3 + (a) long (addr24) (A) long (ear) (A) long (eam) (A) Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 84 To Top / Lineup / Index MB90246A Series Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ Add/Subtract (Byte, Word, Long) [42 Instructions] B Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C RMW * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - * * - - - - - - - - 2 0 3 (b) 2 0 3 + (a) (b) 2 0 3 + (a) 2 x (b) 2 0 2 0 3 + (a) (b) 3 0 2 0 3 (b) 2 0 3 + (a) (b) 2 0 3 + (a) 2 x (b) 2 0 2 0 3 + (a) (b) 3 0 2 0 2 0 3 + (a) (c) 2 0 2 0 3 + (a) 2 x (c) 2 0 3 + (a) (c) 2 0 2 0 3 + (a) (c) 2 0 2 0 3 + (a) 2 x (c) 2 0 3 + (a) (c) 0 (d) 0 0 (d) 0 byte (A) (AH) + (AL) + (C) (decimal) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL A, ear A, eam A, #imm32 word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) - (ear) + (A) word (eam) - (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32 A, ear A, eam A, #imm32 2 5 2 + 6 + (a) 5 4 2 5 2 + 6 + (a) 5 4 Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 85 To Top / Lineup / Index MB90246A Series Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam # Increment/Decrement (Byte, Word, Long) [12 Instructions] ~ B Operation LH AH I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C RMW - - - - - - - - - - - - * * * * * * * * - * * * 2 2 0 byte (ear) (ear) +1 2 + 3 + (a) 2 x (b) byte (eam) (eam) +1 2 2 0 byte (ear) (ear) -1 2 + 3 + (a) 2 x (b) byte (eam) (eam) -1 2 2 0 word (ear) (ear) +1 2 + 3 + (a) 2 x (c) word (eam) (eam) +1 2 2 0 word (ear) (ear) -1 - - - - - - - - - - - - - - - - - - - - - - - - DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam 2 + 3 + (a) 2 x (c) word (eam) (eam) -1 2 4 0 long (ear) (ear) +1 2 + 5 + (a) 2 x (d) long (eam) (eam) +1 2 4 0 long (ear) (ear) -1 2 + 5 + (a) 2 x (d) long (eam) (eam) -1 Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # ~ Compare (Byte, Word, Long) [11 Instructions] B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 word (A) - (ear) word (A) - (eam) word (A) - imm32 LH AH I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C RMW * * * * * * * * * * * - - - - - - - - - - - 1 1 2 2 2 + 3 + (a) 2 2 1 1 2 2 2 + 3 + (a) 3 2 2 6 2 + 7 + (a) 5 3 - - - - - - - - - - - - - - - - - - - - - - Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 86 To Top / Lineup / Index MB90246A Series Table 12 Mnemonic DIVU DIVU DIVU DIVUW DIVUW A A, ear A, eam A, ear A, eam # 1 2 ~ *1 *2 Unsigned Multiply/Division (Word, Long) [11 Instructions] B 0 Operation LH AH I - - - - - S - - - - - T - - - - - N - - - - - Z - - - - - V * * * * * C RMW * * * * * - - - - - 2 + *3 2 2+ *4 *5 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) - - - - - - - - - - MULU MULU MULU MULUW MULUW MULUW A A, ear A, eam A A, ear A, eam 1 2 2+ 1 2 2+ *8 0 byte (AH) byte (AL) word (A) *9 0 byte (A) byte (ear) word (A) *10 (b) byte (A) byte (eam) word (A) *11 0 word (AH) word (AL) long (A) *12 0 word (A) word (ear) long (A) *13 (c) word (A) word (eam) long (A) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note: For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation. *2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation. *3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation. *4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation. *5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero. *9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero. *10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero. *11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero. *12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero. *13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero. 87 To Top / Lineup / Index MB90246A Series Table 13 Mnemonic DIV A # 2 Signed multiplication/division (Word, Long) [11 Instructions] ~ *1 B Operation 0 word (AH)/byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 byte (AH) x byte (AL) word (A) 0 byte (A) x byte (ear) word (A) (b) byte (A) x byte (eam) word (A) 0 word (AH) x word (AL) long (A) 0 word (A) x word (ear) long (A) (b) word (A) x word (eam) long (A) LH AH Z - I - S - T - N - Z - V * C RMW * - DIV A, ear 2 *2 Z - - - - - - * * - DIV A, eam 2 + *3 Z - - - - - - * * - DIVW A, ear 2 *4 - - - - - - - * * - DIVW A, eam 2 + *5 - - - - - - - * * - MUL MUL MUL MULW MULW MULW A A, ear A, eam A A, ear A, eam 2 2 2+ 2 2 2+ *8 *9 *10 *11 *12 *13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - For (b) and (c), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation. *5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: Set to (b) when the division-by-0 or an overflow, and 2 x (b) for normal operation. *7: Set to (c) when the division-by-0 or an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. *1: *2: *3: *4: 88 To Top / Lineup / Index MB90246A Series Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # ~ B Logic 1 (Byte, Word) [39 Instructions] Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - - - * * - - - * * - * * - - - - * * - - - - * * - - - - * * - * * 2 2 0 2 2 0 2 + 3 + (a) (b) 2 3 0 2 + 3 + (a) 2 x (b) 2 2 0 2 2 0 2 + 3 + (a) (b) 2 3 0 2 + 3 + (a) 2 x (b) 2 2 0 2 2 0 2 + 3 + (a) (b) 2 3 0 2 + 3 + (a) 2 x (b) 1 2 0 2 2 0 2 + 3 + (a) 2 x (b) 1 2 0 3 2 0 2 2 0 2 + 3 + (a) (c) 2 3 0 2 + 3 + (a) 2 x (c) 1 2 0 3 2 0 2 2 0 2 + 3 + (a) (c) 2 3 0 2 + 3 + (a) 2 x (c) 1 2 0 3 2 0 2 2 0 2 + 3 + (a) (c) 2 3 0 2 + 3 + (a) 2 x (c) 1 2 0 2 3 0 2 + 3 + (a) 2 x (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note: For (a) to (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 89 To Top / Lineup / Index MB90246A Series Table 15 Mnemonic ANDL ANDL ORL ORL XORL XORL A, ear A, eam A, ear A, eam A, ear A, eam # ~ B 0 (d) 0 (d) 0 (d) Logic 2 (Long) [6 Instructions] Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RMW - - - - - - - - - - - - 2 5 2 + 6 + (a) 2 5 2 + 6 + (a) 2 5 2 + 6 + (a) - - - - - - - - - - - - Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2 RG Sign Reverse (Byte, Word) [6 Instructions] B 0 Operation byte (A) 0 - (A) LH AH I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C * * * * * * RMW 0 X - - - - - - - - - - - - - * - - * 2 3 2 0 byte (ear) 0 - (ear) 2 + 5 + (a) 0 2 x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam 2 3 2 2 + 5 + (a) 0 0 word (ear) 0 - (ear) 2 x (c) word (eam) 0 - (eam) Note: For (a) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Table 17 Mnemonic ABS A ABSW A ABSL A # 2 2 2 ~ 2 2 4 Absolute Values (Byte, Word, Long) [3 Instructions] B 0 0 0 Table 18 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 Operation byte (A) Absolute value (A) word (A) Absolute value (A) long (A) Absolute value (A) LH AH I - - - S - - - T - - - N * * * Z * * * V * * * C RMW - - - - - - Z - - - - - Normalize Instruction (Long) [1 Instruction] B 0 Operation long (A) Shift to where "1" is originally located byte (R0) Number of shifts in the operation LH AH I - S - T - N - Z * V - C - RMW - - - * : Set to 5 when the accumulator is all "0", otherwise set to 5 + (R0). 90 To Top / Lineup / Index MB90246A Series Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0 A, #imm8 A, #imm8 A, #imm8 Shift Type Instruction (Byte, Word, Long) [27 Instructions] B 0 0 Operation byte (A) With right-rotate carry byte (A) With left-rotate carry byte (ear) With right-rotate carry byte (eam) With right-rotate carry byte (ear) With left-rotate carry byte (eam) With left-rotate carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) byte (A) Arithmetic right barrel shift (A, imm8) # 2 2 2 2+ 2 2+ 2 2 2 3 3 3 ~ 2 2 2 3 + (a) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * - - - - - - - - - - - - - - - - - - - - - 2 3 + (a) 0 2 x (b) 0 2 x (b) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1 *1 *1 *3 *3 *3 2 2 2 *1 *1 *1 *3 *3 *3 *2 *2 *2 *4 *4 *4 byte (A) Logical right barrel shift (A, imm8) byte (A) Logical left barrel shift (A, imm8) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) word (A) Arithmetic right barrel shift (A, imm8) ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 ** *R -* * * - * * - * * - * * - * * * * * * * * * * * * ASRW A, #imm8 3 LSRW A, #imm8 3 LSLW A, #imm8 3 ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 word (A) Logical right barrel shift (A, imm8) word (A) Logical left barrel shift (A, imm8) long (A) Arithmetic right barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) long (A) Arithmetic right barrel shift (A, imm8) ASRL A, #imm8 3 LSRL A, #imm8 3 LSLL A, #imm8 3 long (A) Logical right barrel shift (A, imm8) long (A) Logical left barrel shift (A, imm8) Note: For (a) and (b), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: Set to 3 when R0 is 0, otherwise 3 + (R0). Set to 3 when R0 is 0, otherwise 4 + (R0). Set to 3 when imm8 is 0, otherwise 3 + imm8. Set to 3 when imm8 is 0, otherwise 4 + imm8. 91 To Top / Lineup / Index MB90246A Series Table 20 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP @A Branch 1 [31 Instructions] Operation LH AH # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Branch if (Z) = 1 Branch if (Z) = 0 Branch if (C) = 1 Branch if (C) = 0 Branch if (N) = 1 Branch if (N) = 0 Branch if (V) = 1 Branch if (V) = 0 Branch if (T) = 1 Branch if (T) = 0 Branch if (V) xor (N) = 1 Branch if (V) xor (N) = 0 Branch if ((V) xor (N)) or (Z) = 1 Branch if ((V) xor (N)) or (Z) = 0 Branch if (C) or (Z) = 1 Branch if (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 @eam *6 addr24 *7 1 2 3 2 2 3 2 + 4 + (a) 2 3 2 + 4 + (a) 4 3 word (PC) (ear), (PCB) (ear + 2) word (PC) (eam), (PCB) (eam + 2) 2 4 (c) 2 + 5 + (a) 2 x (c) 3 5 (c) 1 5 2 x (c) 2 7 2 x (c) 2 + 8 + (a) 4 7 *2 2 x (c) word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 - 15 (PCB) (ear) 16 - 23 word (PC) (eam) 0 - 15 (PCB) (eam) 16 - 23 word (PC) addr0 - 15, (PCB) addr16 - 23 Note: For (a), (c) and (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: *5: *6: *7: Set to 3 when branch is executed, and 2 when branch is not executed. 3 x (c) + (b) Reads (word) of the branch destination address. W pushes to stack (word), and R reads (word) of the branch destination address. Pushes to stack (word). W pushes to stack (long), and R reads (long) of the branch destination address. Pushes to stack (long). 92 To Top / Lineup / Index MB90246A Series Table 21 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ ear, #imm8, rel eam, #imm8, rel ear, #imm16, rel eam, #imm16, rel ear, rel eam, rel # ~ B 0 0 0 (b) 0 (c) 0 Branch 2 [20 Instructions] Operation Branch if word (A) imm16 LH AH I - - - - - - - - - - R R R R * * - S - - - - - - - - - - S S S S * * - T - - - - - - - - - - - - - - * * - N * * * * * * * * * * - - - - * * - Z * * * * * * * * * * - - - - * * - V * * * * * * * * * * - - - - * * - C RMW * * * * * * - - - - - - - - * * - - - - - - - - * - * - - - - - - - 3 *1 4 *1 4 4+ 5 5+ *1 *3 *1 *3 Branch if byte (A) imm8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Branch if byte (ear) imm8 Branch if byte (eam) imm8 Branch if word (ear) imm16 Branch if word (eam) imm16 byte (ear) = (ear) - 1, Branch if (ear) 0 3 + *4 2 x (b) byte (eam) = (eam) - 1, Branch if (eam) 0 word (ear) = (ear) - 1, Branch if (ear) 0 3 + *4 2 x (c) word (eam) = (eam) - 1, Branch if (eam) 0 2 3 4 1 1 2 2 14 12 13 14 9 11 6 8 x (c) 6 x (c) 6 x (c) 8 x (c) 6 x (c) *5 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt Stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area Restore old frame pointer from stack in the end of the function Return from subroutine Return from subroutine 3 *2 0 3 *2 DWBNZ ear, rel DWBNZ eam, rel INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 LINK #imm8 UNLINK 1 5 (c) - - - - - - - - - - RET *7 RETP *8 1 1 4 5 (c) (d) - - - - - - - - - - - - - - - - - - - - Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: *5: *6: Set to 4 when branch is executed, and 3 when branch is not executed. Set to 5 when branch is executed, and 4 when branch is not executed. Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed. Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed. Set to 3 x (b) + 2 x (c) when an interrupt request is issued, and 6 x (c) for return. This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector. *7: Return from stack (word). *8: Return from stack (long). 93 To Top / Lineup / Index MB90246A Series Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR MOV MOV Miscellaneous Control Types (Byte, Word, Long) [36 Instructions] ~ 3 3 3 *3 3 3 3 *2 9 3 3 2 2 B (c) (c) (c) *4 (c) (c) (c) *4 Operation LH AH # 1 1 1 2 1 1 1 2 1 2 2 2 2 I - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RMW - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - * * * - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A AH PS rlst A AH PS rlst @A CCR, #imm8 CCR, #imm8 word (SP) (SP) - 2, ((SP)) (A) - word (SP) (SP) - 2, ((SP)) (AH) - word (SP) (SP) - 2, ((SP)) (PS) - (PS) (PS) - 2n, ((SP)) (rlst) - word (A) ((SP)), (SP) (SP) + 2 word (AH) ((SP)), (SP) (SP) + 2 word (PS) ((SP)), (SP) (SP) + 2 (rlst) ((SP)), (SP) (SP) + 2n - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - - - - - - - 6 x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam - - - - - - RP #imm8 , ILM, #imm8 MOVEA MOVEA MOVEA MOVEA RWi, ear RWi, eam A, ear A, eam 3 2 2 + 2 + (a) 2 2 2 + 1 + (a) 2 3 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7 ADDSP #imm8 ADDSP #imm16 MOV MOV MOV NOP ADB DTB PCB SPB NCC CMR MOVW SPCU, #imm16 MOVW SPCL, #imm16 word (SP) (SP) + ext (imm8) - - word (SP) (SP) + imm16 byte (A) (brgl) byte (brg2) (A) byte (brg2) imm8 No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no change in flag Prefix for common register bank A, brgl 2 brg2, A 2 brg2, #imm8 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 Z - - - - - - - - - - - - - Z Z Z SETSPC CLRSPC BTSCN A BTSCNS A BTSCND A word (SPCU) (imm16) word (SPCL) (imm16) Enables stack check operation. Disables stack check operation. Bit position of 1 in byte (A) from word (A) Bit position (x 2) of 1 in byte (A) from word (A) Bit position (x 4) of 1 in byte (A) from word (A) Note: For (a) and (c), refer to "Table 4 Number of Execution Cycles in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB : 2 states DPR : 3 states *2: 3 + 4 x (number of POPs) *3: 3 + 4 x (number of PUSHes) *4: (Number of POPs) x (c), or (number of PUSHes) x (c) 94 To Top / Lineup / Index MB90246A Series *5: Set to 3 when AL is 0, 5 when AL is not 0. *6: Set to 4 when AL is 0, 6 when AL is not 0. *7: Set to 5 when AL is 0, 7 when AL is not 0. Table 23 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 Bit Manipulation Instruction [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I - - - - - - - - - - - - - - - - - - - - - S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - Z Z Z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - 2 x (b) bit (dir:bp) b (A) 2 x (b) bit (addr16:bp) b (A) 2 x (b) bit (io:bp) b (A) 2 x (b) bit (dir:bp) b 1 2 x (b) bit (addr16:bp) b 1 2 x (b) bit (io:bp) b 1 2 x (b) bit (dir:bp) b 0 2 x (b) bit (addr16:bp) b 0 2 x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch if (dir:bp) b = 0 Branch if (addr16:bp) b = 0 Branch if (io:bp) b = 0 Branch if (dir:bp) b = 1 Branch if (addr16:bp) b = 1 Branch if (io:bp) b = 1 SBBS addr16:bp, rel WBTS io:bp WBTC io:bp 2 x (b) Branch if (addr16:bp) b = 1, bit = 1 *4 *4 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 Note: For (b), refer to "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." *1: *2: *3: *4: Set to 5 when branch is executed, and 4 when branch is not executed. 7 if conditions are met, 6 when conditions are not met. Indeterminate times Until conditions are met 95 To Top / Lineup / Index MB90246A Series Table 24 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instruction (Byte, Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 B 0 0 0 0 0 0 Operation byte (A) 0 - 7 (A) 8 - 15 word (AH) (AL) byte sign-extension word sign-extension byte zero-extension word zero-extension LH AH I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C RMW - - - - - - - - - - - - - - X - Z - - * - X - Z Table 25 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI # 2 2 2 2 ~ *2 *2 *1 *1 B String Instruction [10 Instructions] Operation LH AH I - - - - - - - - - - S - - - - - - - - - - T - - - - - - - - - - N - - * * * - - * * * Z - - * * * - - * * * V - - * * - - - * * - C RMW - - * * - - - * * - - - - - - - - - - - *3 byte transfer @AH + @AL +, Counter = RW0 *3 byte transfer @AH - @AL -, Counter = RW0 *4 byte search (@AH +) - AL, Counter = RW0 *4 byte search (@AH -) - AL, Counter = RW0 - - - - - - - - - - - - - - - - - - - - 2 5m + 6 *5 byte fill @AH + AL, Counter = RW0 2 2 2 2 *2 *2 *1 *1 *6 word transfer @AH + @AL +, Counter = RW0 *6 word transfer @AH - @AL -, Counter = RW0 *7 word search (@AH +) - AL, Counter = RW0 *7 word search (@AH -) - AL, Counter = RW0 2 5m + 6 *8 word fill @AH + AL, Counter = RW0 m: RW0 value (counter value) *1: *2: *3: *4: *5: *6: *7: *8: 3 when RW0 is 0, 2 + 6 x (RW0) when count out, and 6n + 4 when matched 4 when RW0 is 0, otherwise 2 + 6 x (RW0) (b) x (RW0) (b) x n (b) x (RW0) (c) x (RW0) (c) x n (c) x (RW0) 96 To Top / Lineup / Index MB90246A Series Table 26 Mnemonic MOVM @A, @RLi, #imm8 MOVM @A, eam, #imm8 MOVM addr16, @RLi, #imm8 # 3 3+ 5 Multiple Data Transfer Instructions [18 Instruction] ~ *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 B Operation *3 Multiple data transfer byte ((A)) ((RLi)) *3 Multiple data transfer byte ((A)) (eam) *3 Multiple data transfer byte (addr16) ((RLi)) *3 Multiple data transfer byte (addr16) (eam) *4 Multiple data transfer word ((A)) ((RLi)) *4 Multiple data transfer word ((A)) (eam) *4 Multiple data transfer word (addr16) ((RLi)) *4 Multiple data transfer word (addr16) (eam) *3 Multiple data transfer byte ((RLi)) ((A)) *3 Multiple data transfer byte (eam) ((A)) *3 Multiple data transfer byte ((RLi)) (addr16) *3 Multiple data transfer byte (eam) (addr16) *4 Multiple data transfer word ((RLi)) ((A)) *4 Multiple data transfer word (eam) ((A)) *4 Multiple data transfer word ((RLi)) (addr16) *4 Multiple data transfer word (eam) (addr16) *3 Multiple data transfer byte (bnk: addr16) (bnk: addr16) *4 Multiple data transfer word (bnk: addr16) (bnk: addr16) LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - N - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - - - - - - V - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVM addr16, @eam, #imm8 5 + MOVMW@A, @RLi, #imm8 MOVMW@A, eam, #imm8 MOVMWaddr16, @RLi, #imm8 3 3+ 5 MOVMWaddr16, @eam, #imm8 5 + MOVM @RLi, @A, #imm8 MOVM @eam, A, #imm8 MOVM @RLi, addr16, #imm8 3 3+ 5 MOVM @eam, addr16, #imm8 5 + MOVMW@RLi, @A, #imm8 MOVMW@eam, A, #imm8 MOVMW@RLi, addr16, #imm8 3 3+ 5 MOVMW@eam, addr16, #imm8 5 + MOVM bnk: addr16, bnk: addr16, #imm8*5 MOVMWbnk: addr16, 7 7 *1 - - - - - - - - - - bnk: addr16, #imm8*5 *1: *2: *3: *4: *5: 256 when 5 + imm8 x 5, imm8 is 0. 256 when 5 + imm8 x 5 + (a), imm8 is 0. (Number of transfer cycles) x (b) x 2 (Number of transfer cycles) x (c) x 2 The bank register specified by bnk is the same as that for the MOVS instruction. 97 To Top / Lineup / Index MB90246A Series s ORDERING INFORMATION Part number MB90246APFV Package 100-pin Plastic LQFP (FPT-100P-M05) Remarks 98 To Top / Lineup / Index MB90246A Series s PACKAGE DIMENSIONS 100-pin Plastic LQFP (FPT-100P-M05) 16.000.20(.630.008)SQ 75 14.000.10(.551.004)SQ 51 1.50 -0.10 (Mounting height) +.008 .059 -.004 +0.20 76 50 12.00 (.472) REF INDEX 15.00 (.591) NOM Details of "A" part 0.15(.006) 100 26 0.15(.006) 0.15(.006)MAX LEAD No. 1 25 "B" +0.05 "A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001 +0.08 0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001 0.08(.003) M Details of "B" part 0.100.10 (STAND OFF) (.004.004) 0.10(.004) 0.500.20(.020.008) 0~10 C 1995 FUJITSU LIMITED F100007S-2C-3 Dimensions in mm (inches) 99 To Top / Lineup / Index MB90246A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F98010 (c) FUJITSU LIMITED Printed in Japan 100 |
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